URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 10 and 11

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Rev 10	Rev 11
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2002/12/28 04:13:23 mohor`
	`// Backup version.`
	`//`
`// Revision 1.5 2002/12/27 00:12:52 mohor`	`// Revision 1.5 2002/12/27 00:12:52 mohor`
`// Header changed, testbench improved to send a frame (crc still missing).`	`// Header changed, testbench improved to send a frame (crc still missing).`
`//`	`//`
`// Revision 1.4 2002/12/26 01:33:05 mohor`	`// Revision 1.4 2002/12/26 01:33:05 mohor`
`// Tripple sampling supported.`	`// Tripple sampling supported.`
Line 89...	Line 92...
`/* Output signals from this module */`	`/* Output signals from this module */`
`clk_en,`	`clk_en,`
`sample_point,`	`sample_point,`
`sampled_bit,`	`sampled_bit,`
`sampled_bit_q,`	`sampled_bit_q,`
	`hard_sync,`
	`resync,`

`/* Output from can_bsp module */`	`/* Output from can_bsp module */`
`rx_idle`	`rx_idle`





`);`	`);`

`parameter Tp = 1;`	`parameter Tp = 1;`

`input clk;`	`input clk;`
Line 124...	Line 130...
`/* Output signals from this module */`	`/* Output signals from this module */`
`output clk_en;`	`output clk_en;`
`output sample_point;`	`output sample_point;`
`output sampled_bit;`	`output sampled_bit;`
`output sampled_bit_q;`	`output sampled_bit_q;`
	`output hard_sync;`
	`output resync;`



`reg [8:0] clk_cnt;`	`reg [8:0] clk_cnt;`
`reg clk_en;`	`reg clk_en;`
Line 145...	Line 153...

`wire go_sync;`	`wire go_sync;`
`wire go_seg1;`	`wire go_seg1;`
`wire go_seg2;`	`wire go_seg2;`
`wire [8:0] preset_cnt;`	`wire [8:0] preset_cnt;`
`wire hard_sync;`
`wire resync;`
`wire sync_window;`	`wire sync_window;`



`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`	`assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2`

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 10 and 11