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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 31 and 35
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| Rev 31 |
Rev 35 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/02/11 00:56:06 mohor
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// Wishbone interface added.
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//
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// Revision 1.9 2003/02/09 02:24:33 mohor
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// Revision 1.9 2003/02/09 02:24:33 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// Bosch license warning added. Error counters finished. Overload frames
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// still need to be fixed.
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// still need to be fixed.
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//
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//
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// Revision 1.8 2003/01/31 01:13:38 mohor
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// Revision 1.8 2003/01/31 01:13:38 mohor
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| Line 101... |
Line 104... |
addr,
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addr,
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data_out,
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data_out,
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reset_mode,
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reset_mode,
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release_buffer,
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release_buffer,
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extended_mode
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extended_mode,
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overrun,
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info_empty
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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Line 122... |
input reset_mode;
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input reset_mode;
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input release_buffer;
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input release_buffer;
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input extended_mode;
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input extended_mode;
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output [7:0] data_out;
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output [7:0] data_out;
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output overrun;
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output info_empty;
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reg [7:0] fifo [0:63];
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reg [7:0] fifo [0:63];
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reg [5:0] rd_pointer;
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reg [5:0] rd_pointer;
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reg [5:0] wr_pointer;
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reg [5:0] wr_pointer;
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| Line 137... |
Line 144... |
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wire write_length_info;
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wire write_length_info;
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wire fifo_empty;
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wire fifo_empty;
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wire fifo_full;
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wire fifo_full;
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wire info_full;
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wire info_full;
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wire info_empty;
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assign write_length_info = (~wr) & wr_q;
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assign write_length_info = (~wr) & wr_q;
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// Delayed write signal
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// Delayed write signal
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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Line 199... |
if (write_length_info & (~info_full))
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if (write_length_info & (~info_full))
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overrun_info[wr_info_pointer] <=#Tp latch_overrun | (wr & fifo_full);
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overrun_info[wr_info_pointer] <=#Tp latch_overrun | (wr & fifo_full);
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end
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end
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// reading overrun
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assign overrun = overrun_info[rd_info_pointer];
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// rd_info_pointer
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// rd_info_pointer
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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