| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.26 2003/06/22 01:33:14 mohor
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// clkout is clk/2 after the reset.
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//
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// Revision 1.25 2003/06/21 12:16:30 mohor
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// Revision 1.25 2003/06/21 12:16:30 mohor
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// paralel_case and full_case compiler directives added to case statements.
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// paralel_case and full_case compiler directives added to case statements.
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//
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//
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// Revision 1.24 2003/06/09 11:22:54 mohor
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// Revision 1.24 2003/06/09 11:22:54 mohor
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// data_out is already registered in the can_top.v file.
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// data_out is already registered in the can_top.v file.
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| Line 733... |
Line 736... |
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always @ (cd)
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always @ (cd)
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begin
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begin
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case (cd) /* synthesis full_case synthesis parallel_case */
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case (cd) /* synthesis full_case parallel_case */
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3'b000 : clkout_div <= 0;
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3'b000 : clkout_div <= 0;
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3'b001 : clkout_div <= 1;
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3'b001 : clkout_div <= 1;
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3'b010 : clkout_div <= 2;
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3'b010 : clkout_div <= 2;
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3'b011 : clkout_div <= 3;
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3'b011 : clkout_div <= 3;
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3'b100 : clkout_div <= 4;
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3'b100 : clkout_div <= 4;
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| Line 1026... |
Line 1029... |
begin
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begin
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if(read) // read
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if(read) // read
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begin
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begin
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if (extended_mode) // EXTENDED mode (Different register map depends on mode)
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if (extended_mode) // EXTENDED mode (Different register map depends on mode)
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begin
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begin
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case(addr) /* synthesis full_case synthesis parallel_case */
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case(addr) /* synthesis full_case parallel_case */
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8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
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8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
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8'd1 : data_out <= 8'h0;
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8'd1 : data_out <= 8'h0;
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8'd2 : data_out <= status;
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8'd2 : data_out <= status;
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8'd3 : data_out <= irq_reg;
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8'd3 : data_out <= irq_reg;
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8'd4 : data_out <= irq_en_ext;
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8'd4 : data_out <= irq_en_ext;
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Line 1057... |
8'd26 : data_out <= 8'h0;
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8'd26 : data_out <= 8'h0;
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8'd27 : data_out <= 8'h0;
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8'd27 : data_out <= 8'h0;
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8'd28 : data_out <= 8'h0;
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8'd28 : data_out <= 8'h0;
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8'd29 : data_out <= {1'b0, rx_message_counter};
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8'd29 : data_out <= {1'b0, rx_message_counter};
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8'd31 : data_out <= clock_divider;
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8'd31 : data_out <= clock_divider;
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default: data_out <= 8'h0;
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endcase
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endcase
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end
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end
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else // BASIC mode
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else // BASIC mode
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begin
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begin
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case(addr) /* synthesis full_case synthesis parallel_case */
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case(addr) /* synthesis full_case parallel_case */
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8'd0 : data_out <= {3'b001, mode_basic[4:1], mode[0]};
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8'd0 : data_out <= {3'b001, mode_basic[4:1], mode[0]};
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8'd1 : data_out <= 8'hff;
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8'd1 : data_out <= 8'hff;
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8'd2 : data_out <= status;
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8'd2 : data_out <= status;
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8'd3 : data_out <= {4'hf, irq_reg[3:0]};
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8'd3 : data_out <= {4'hf, irq_reg[3:0]};
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8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
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8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
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Line 1081... |
8'd16 : data_out <= reset_mode? 8'hff : tx_data_6;
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8'd16 : data_out <= reset_mode? 8'hff : tx_data_6;
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8'd17 : data_out <= reset_mode? 8'hff : tx_data_7;
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8'd17 : data_out <= reset_mode? 8'hff : tx_data_7;
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8'd18 : data_out <= reset_mode? 8'hff : tx_data_8;
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8'd18 : data_out <= reset_mode? 8'hff : tx_data_8;
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8'd19 : data_out <= reset_mode? 8'hff : tx_data_9;
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8'd19 : data_out <= reset_mode? 8'hff : tx_data_9;
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8'd31 : data_out <= clock_divider;
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8'd31 : data_out <= clock_divider;
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default: data_out <= 8'h0;
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endcase
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endcase
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end
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end
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end
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end
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else
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else
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data_out <= 8'h0;
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data_out <= 8'h0;
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