OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 102 and 104

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 102 Rev 104
Line 48... Line 48...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.37  2003/07/07 11:21:37  mohor
 
// Little fixes (to fix warnings).
 
//
// Revision 1.36  2003/07/03 09:32:20  mohor
// Revision 1.36  2003/07/03 09:32:20  mohor
// Synchronization changed.
// Synchronization changed.
//
//
// Revision 1.35  2003/06/27 20:56:12  simons
// Revision 1.35  2003/06/27 20:56:12  simons
// Virtual silicon ram instances added.
// Virtual silicon ram instances added.
Line 208... Line 211...
  release_buffer,
  release_buffer,
  tx_request,
  tx_request,
  abort_tx,
  abort_tx,
  self_rx_request,
  self_rx_request,
  single_shot_transmission,
  single_shot_transmission,
 
  tx_state,
 
  tx_state_q,
 
 
  /* Arbitration Lost Capture Register */
  /* Arbitration Lost Capture Register */
  read_arbitration_lost_capture_reg,
  read_arbitration_lost_capture_reg,
 
 
  /* Error Code Capture Register */
  /* Error Code Capture Register */
Line 231... Line 236...
  extended_mode,
  extended_mode,
 
 
  rx_idle,
  rx_idle,
  transmitting,
  transmitting,
  go_rx_inter,
  go_rx_inter,
  last_bit_of_inter,
  not_first_bit_of_inter,
  set_reset_mode,
  set_reset_mode,
  node_bus_off,
  node_bus_off,
  error_status,
  error_status,
  rx_err_cnt,
  rx_err_cnt,
  tx_err_cnt,
  tx_err_cnt,
Line 331... Line 336...
input         release_buffer;
input         release_buffer;
input         tx_request;
input         tx_request;
input         abort_tx;
input         abort_tx;
input         self_rx_request;
input         self_rx_request;
input         single_shot_transmission;
input         single_shot_transmission;
 
output        tx_state;
 
output        tx_state_q;
 
 
/* Arbitration Lost Capture Register */
/* Arbitration Lost Capture Register */
input         read_arbitration_lost_capture_reg;
input         read_arbitration_lost_capture_reg;
 
 
/* Error Code Capture Register */
/* Error Code Capture Register */
Line 351... Line 358...
input         we_tx_err_cnt;
input         we_tx_err_cnt;
 
 
output        rx_idle;
output        rx_idle;
output        transmitting;
output        transmitting;
output        go_rx_inter;
output        go_rx_inter;
output        last_bit_of_inter;
output        not_first_bit_of_inter;
output        set_reset_mode;
output        set_reset_mode;
output        node_bus_off;
output        node_bus_off;
output        error_status;
output        error_status;
output  [8:0] rx_err_cnt;
output  [8:0] rx_err_cnt;
output  [8:0] tx_err_cnt;
output  [8:0] tx_err_cnt;
Line 497... Line 504...
reg     [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
reg     [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
 
 
reg     [5:0] tx_pointer;
reg     [5:0] tx_pointer;
reg           tx_bit;
reg           tx_bit;
reg           tx_state;
reg           tx_state;
 
reg           tx_state_q;
reg           transmitter;
reg           transmitter;
reg           finish_msg;
reg           finish_msg;
 
 
reg     [8:0] rx_err_cnt;
reg     [8:0] rx_err_cnt;
reg     [8:0] tx_err_cnt;
reg     [8:0] tx_err_cnt;
Line 555... Line 563...
wire          go_rx_eof;
wire          go_rx_eof;
wire          go_overload_frame;
wire          go_overload_frame;
wire          go_rx_inter;
wire          go_rx_inter;
wire          go_error_frame;
wire          go_error_frame;
 
 
 
wire          last_bit_of_inter;
 
 
wire          go_crc_enable;
wire          go_crc_enable;
wire          rst_crc_enable;
wire          rst_crc_enable;
 
 
wire          bit_de_stuff_set;
wire          bit_de_stuff_set;
wire          bit_de_stuff_reset;
wire          bit_de_stuff_reset;
Line 674... Line 684...
assign bit_err_exc5 = (error_frame & (error_cnt2 == 7)) | (overload_frame & (overload_cnt2 == 7));
assign bit_err_exc5 = (error_frame & (error_cnt2 == 7)) | (overload_frame & (overload_cnt2 == 7));
 
 
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
 
 
assign last_bit_of_inter = rx_inter & (bit_cnt == 2);
assign last_bit_of_inter = rx_inter & (bit_cnt == 2);
 
assign not_first_bit_of_inter = rx_inter & (bit_cnt != 0);
 
 
 
 
// Rx idle state
// Rx idle state
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
Line 1685... Line 1696...
  else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
  else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
    tx_pointer <=#Tp tx_pointer + 1'b1;
    tx_pointer <=#Tp tx_pointer + 1'b1;
end
end
 
 
 
 
assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost) | single_shot_transmission);
//assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost) | single_shot_transmission);
 
assign tx_successful = transmitter & go_rx_inter & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
 
 
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    need_to_tx <= 1'b0;
    need_to_tx <= 1'b0;
  else if (tx_successful | reset_mode | (abort_tx & (~transmitting)))
  else if (tx_successful | reset_mode | (abort_tx & (~transmitting)) | ((~tx_state) & tx_state_q & single_shot_transmission))
    need_to_tx <=#Tp 1'h0;
    need_to_tx <=#Tp 1'h0;
  else if (tx_request & sample_point)
  else if (tx_request & sample_point)
    need_to_tx <=#Tp 1'b1;
    need_to_tx <=#Tp 1'b1;
end
end
 
 
Line 1728... Line 1740...
    tx_state <=#Tp 1'b0;
    tx_state <=#Tp 1'b0;
  else if (go_tx)
  else if (go_tx)
    tx_state <=#Tp 1'b1;
    tx_state <=#Tp 1'b1;
end
end
 
 
 
always @ (posedge clk)
 
begin
 
  tx_state_q <=#Tp tx_state;
 
end
 
 
 
 
 
 
// Node is a transmitter
// Node is a transmitter
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    transmitter <= 1'b0;
    transmitter <= 1'b0;
  else if (go_tx)
  else if (go_tx)
    transmitter <=#Tp 1'b1;
    transmitter <=#Tp 1'b1;
  else if (reset_mode | go_rx_inter)
  else if ((reset_mode | go_rx_inter ) | ((~tx_state) & tx_state_q))
    transmitter <=#Tp 1'b0;
    transmitter <=#Tp 1'b0;
end
end
 
 
 
 
 
 
Line 1869... Line 1886...
    rx_err_cnt <=#Tp 'h0;
    rx_err_cnt <=#Tp 'h0;
  else
  else
    begin
    begin
      if (~listen_only_mode)
      if (~listen_only_mode)
        begin
        begin
          if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
          if ((~transmitter) & rx_ack & (~err) & (rx_err_cnt > 0))
            begin
            begin
              if (rx_err_cnt > 127)
              if (rx_err_cnt > 127)
                rx_err_cnt <=#Tp 127;
                rx_err_cnt <=#Tp 127;
              else
              else
                rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
                rx_err_cnt <=#Tp rx_err_cnt - 1'b1;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.