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Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.19 2003/07/03 09:30:44 mohor
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// PCI_BIST replaced with CAN_BIST.
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//
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// Revision 1.18 2003/06/27 22:14:23 simons
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// Revision 1.18 2003/06/27 22:14:23 simons
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// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
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// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
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//
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//
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// Revision 1.17 2003/06/27 20:56:15 simons
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// Revision 1.17 2003/06/27 20:56:15 simons
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// Virtual silicon ram instances added.
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// Virtual silicon ram instances added.
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| Line 151... |
Line 154... |
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input clk;
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input clk;
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input rst;
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input rst;
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input wr;
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input wr;
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input [7:0] data_in;
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input [7:0] data_in;
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input [7:0] addr;
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input [5:0] addr;
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input reset_mode;
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input reset_mode;
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input release_buffer;
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input release_buffer;
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input extended_mode;
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input extended_mode;
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input fifo_selected;
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input fifo_selected;
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| Line 209... |
Line 212... |
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// Delayed write signal
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// Delayed write signal
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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wr_q <= 0;
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wr_q <=#Tp 1'b0;
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else if (reset_mode)
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else if (reset_mode)
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wr_q <=#Tp 0;
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wr_q <=#Tp 1'b0;
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else
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else
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wr_q <=#Tp wr;
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wr_q <=#Tp wr;
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end
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end
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// length counter
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// length counter
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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len_cnt <= 0;
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len_cnt <= 4'h0;
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else if (reset_mode | write_length_info)
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else if (reset_mode | write_length_info)
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len_cnt <=#Tp 1'b0;
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len_cnt <=#Tp 4'h0;
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else if (wr & (~fifo_full))
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else if (wr & (~fifo_full))
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len_cnt <=#Tp len_cnt + 1'b1;
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len_cnt <=#Tp len_cnt + 1'b1;
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end
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end
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// wr_info_pointer
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// wr_info_pointer
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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wr_info_pointer <= 0;
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wr_info_pointer <= 6'h0;
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else if (write_length_info & (~info_full) | initialize_memories)
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else if (write_length_info & (~info_full) | initialize_memories)
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wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
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wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
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else if (reset_mode)
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else if (reset_mode)
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wr_info_pointer <=#Tp 0;
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wr_info_pointer <=#Tp 6'h0;
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end
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end
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// rd_info_pointer
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// rd_info_pointer
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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rd_info_pointer <= 0;
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rd_info_pointer <= 6'h0;
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else if (reset_mode)
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else if (reset_mode)
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rd_info_pointer <=#Tp 0;
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rd_info_pointer <=#Tp 6'h0;
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else if (release_buffer & (~fifo_empty))
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else if (release_buffer & (~fifo_empty))
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rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
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rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
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end
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end
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// rd_pointer
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// rd_pointer
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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rd_pointer <= 0;
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rd_pointer <= 5'h0;
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else if (release_buffer & (~fifo_empty))
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else if (release_buffer & (~fifo_empty))
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rd_pointer <=#Tp rd_pointer + length_info;
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rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
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else if (reset_mode)
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else if (reset_mode)
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rd_pointer <=#Tp 0;
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rd_pointer <=#Tp 5'h0;
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end
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end
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// wr_pointer
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// wr_pointer
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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wr_pointer <= 0;
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wr_pointer <= 5'h0;
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else if (wr & (~fifo_full))
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else if (wr & (~fifo_full))
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wr_pointer <=#Tp wr_pointer + 1'b1;
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wr_pointer <=#Tp wr_pointer + 1'b1;
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else if (reset_mode)
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else if (reset_mode)
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wr_pointer <=#Tp 0;
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wr_pointer <=#Tp 5'h0;
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end
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end
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// latch_overrun
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// latch_overrun
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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latch_overrun <= 0;
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latch_overrun <= 1'b0;
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else if (reset_mode | write_length_info)
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else if (reset_mode | write_length_info)
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latch_overrun <=#Tp 0;
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latch_overrun <=#Tp 1'b0;
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else if (wr & fifo_full)
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else if (wr & fifo_full)
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latch_overrun <=#Tp 1'b1;
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latch_overrun <=#Tp 1'b1;
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end
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end
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// Counting data in fifo
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// Counting data in fifo
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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fifo_cnt <= 0;
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fifo_cnt <= 7'h0;
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else if (wr & (~release_buffer) & (~fifo_full))
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else if (wr & (~release_buffer) & (~fifo_full))
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fifo_cnt <=#Tp fifo_cnt + 1'b1;
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fifo_cnt <=#Tp fifo_cnt + 1'b1;
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else if ((~wr) & release_buffer & (~fifo_empty))
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else if ((~wr) & release_buffer & (~fifo_empty))
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fifo_cnt <=#Tp fifo_cnt - length_info;
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fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
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else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
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else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
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fifo_cnt <=#Tp fifo_cnt - length_info + 1'b1;
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fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
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else if (reset_mode)
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else if (reset_mode)
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fifo_cnt <=#Tp 0;
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fifo_cnt <=#Tp 7'h0;
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end
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end
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assign fifo_full = fifo_cnt == 64;
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assign fifo_full = fifo_cnt == 7'd64;
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assign fifo_empty = fifo_cnt == 0;
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assign fifo_empty = fifo_cnt == 7'd0;
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// Counting data in length_fifo and overrun_info fifo
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// Counting data in length_fifo and overrun_info fifo
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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info_cnt <= 0;
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info_cnt <=#Tp 7'h0;
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else if (reset_mode)
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info_cnt <=#Tp 7'h0;
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else if (write_length_info ^ release_buffer)
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else if (write_length_info ^ release_buffer)
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begin
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begin
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if (release_buffer & (~info_empty))
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if (release_buffer & (~info_empty))
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info_cnt <=#Tp info_cnt - 1'b1;
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info_cnt <=#Tp info_cnt - 1'b1;
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else if (write_length_info & (~info_full))
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else if (write_length_info & (~info_full))
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info_cnt <=#Tp info_cnt + 1'b1;
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info_cnt <=#Tp info_cnt + 1'b1;
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end
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end
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end
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end
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assign info_full = info_cnt == 64;
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assign info_full = info_cnt == 7'd64;
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assign info_empty = info_cnt == 0;
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assign info_empty = info_cnt == 7'd0;
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// Selecting which address will be used for reading data from rx fifo
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// Selecting which address will be used for reading data from rx fifo
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always @ (extended_mode or rd_pointer or addr)
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always @ (extended_mode or rd_pointer or addr)
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begin
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begin
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if (extended_mode) // extended mode
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if (extended_mode) // extended mode
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begin
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read_address = rd_pointer + (addr - 6'd16);
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read_address <= rd_pointer + (addr - 8'd16);
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end
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else // normal mode
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else // normal mode
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begin
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read_address = rd_pointer + (addr - 6'd20);
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read_address <= rd_pointer + (addr - 8'd20);
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end
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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initialize_memories <= 1;
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initialize_memories <= 1'b1;
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else if (&wr_info_pointer)
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else if (&wr_info_pointer)
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initialize_memories <=#Tp 1'b0;
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initialize_memories <=#Tp 1'b0;
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end
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end
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