URL
https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_fifo.v] - Diff between revs 97 and 99
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 97 |
Rev 99 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.18 2003/06/27 22:14:23 simons
|
|
// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
|
|
//
|
// Revision 1.17 2003/06/27 20:56:15 simons
|
// Revision 1.17 2003/06/27 20:56:15 simons
|
// Virtual silicon ram instances added.
|
// Virtual silicon ram instances added.
|
//
|
//
|
// Revision 1.16 2003/06/18 23:03:44 mohor
|
// Revision 1.16 2003/06/18 23:03:44 mohor
|
// Typo fixed.
|
// Typo fixed.
|
| Line 490... |
Line 493... |
|
|
|
|
`else
|
`else
|
`ifdef VIRTUALSILICON_RAM
|
`ifdef VIRTUALSILICON_RAM
|
|
|
`ifdef PCI_BIST
|
`ifdef CAN_BIST
|
vs_hdtp_64x8_bist fifo
|
vs_hdtp_64x8_bist fifo
|
`else
|
`else
|
vs_hdtp_64x8 fifo
|
vs_hdtp_64x8 fifo
|
`endif
|
`endif
|
(
|
(
|
| Line 504... |
Line 507... |
.WADR (wr_pointer),
|
.WADR (wr_pointer),
|
.DI (data_in),
|
.DI (data_in),
|
.DOUT (data_out),
|
.DOUT (data_out),
|
.REN (~fifo_selected),
|
.REN (~fifo_selected),
|
.WEN (~(wr & (~fifo_full)))
|
.WEN (~(wr & (~fifo_full)))
|
`ifdef PCI_BIST
|
`ifdef CAN_BIST
|
,
|
,
|
// debug chain signals
|
// debug chain signals
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
|
.scanb_clk (scanb_clk),
|
.scanb_clk (scanb_clk),
|
.scanb_si (scanb_si),
|
.scanb_si (scanb_si),
|
.scanb_so (scanb_s_0),
|
.scanb_so (scanb_s_0),
|
.scanb_en (scanb_en)
|
.scanb_en (scanb_en)
|
`endif
|
`endif
|
);
|
);
|
|
|
`ifdef PCI_BIST
|
`ifdef CAN_BIST
|
vs_hdtp_64x4_bist info_fifo
|
vs_hdtp_64x4_bist info_fifo
|
`else
|
`else
|
vs_hdtp_64x4 info_fifo
|
vs_hdtp_64x4 info_fifo
|
`endif
|
`endif
|
(
|
(
|
| Line 529... |
Line 532... |
.WADR (wr_info_pointer),
|
.WADR (wr_info_pointer),
|
.DI (len_cnt & {4{~initialize_memories}}),
|
.DI (len_cnt & {4{~initialize_memories}}),
|
.DOUT (length_info),
|
.DOUT (length_info),
|
.REN (1'b0),
|
.REN (1'b0),
|
.WEN (~(write_length_info & (~info_full) | initialize_memories))
|
.WEN (~(write_length_info & (~info_full) | initialize_memories))
|
`ifdef PCI_BIST
|
`ifdef CAN_BIST
|
,
|
,
|
// debug chain signals
|
// debug chain signals
|
.scanb_rst (scanb_rst),
|
.scanb_rst (scanb_rst),
|
.scanb_clk (scanb_clk),
|
.scanb_clk (scanb_clk),
|
.scanb_si (scanb_s_0),
|
.scanb_si (scanb_s_0),
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.