URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_top.v] - Diff between revs 110 and 117

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Rev 110	Rev 117
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.42 2003/07/16 15:11:28 mohor`
	`// Fixed according to the linter.`
	`//`
`// Revision 1.41 2003/07/10 15:32:27 mohor`	`// Revision 1.41 2003/07/10 15:32:27 mohor`
`// Unused signal removed.`	`// Unused signal removed.`
`//`	`//`
`// Revision 1.40 2003/07/10 01:59:04 tadejm`	`// Revision 1.40 2003/07/10 01:59:04 tadejm`
`// Synchronization fixed. In some strange cases it didn't work according to`	`// Synchronization fixed. In some strange cases it didn't work according to`
Line 212...	Line 215...
`cs_can_i,`	`cs_can_i,`
`endif	`endif
`clk_i,`	`clk_i,`
`rx_i,`	`rx_i,`
`tx_o,`	`tx_o,`
	`tx_oen_o,`
`irq_on,`	`irq_on,`
`clkout_o`	`clkout_o`

`// Bist`	`// Bist`
`ifdef CAN_BIST	`ifdef CAN_BIST
`,`	`,`
`// debug chain signals`	`// debug chain signals`
`scanb_rst, // bist scan reset`	`scanb_rst, // bist scan reset`
Line 267...	Line 272...
`endif	`endif

`input clk_i;`	`input clk_i;`
`input rx_i;`	`input rx_i;`
`output tx_o;`	`output tx_o;`
	`output tx_oen_o;`
`output irq_on;`	`output irq_on;`
`output clkout_o;`	`output clkout_o;`

`// Bist`	`// Bist`
`ifdef CAN_BIST	`ifdef CAN_BIST
Line 399...	Line 405...
`wire set_arbitration_lost_irq;`	`wire set_arbitration_lost_irq;`
`wire [4:0] arbitration_lost_capture;`	`wire [4:0] arbitration_lost_capture;`
`wire node_error_passive;`	`wire node_error_passive;`
`wire node_error_active;`	`wire node_error_active;`
`wire [6:0] rx_message_counter;`	`wire [6:0] rx_message_counter;`
`wire tx_out;`
`wire tx_oen;`

`wire rst;`	`wire rst;`
`wire we;`	`wire we;`
`wire [7:0] addr;`	`wire [7:0] addr;`
`wire [7:0] data_in;`	`wire [7:0] data_in;`
Line 674...	Line 678...
`.tx_data_11(tx_data_11),`	`.tx_data_11(tx_data_11),`
`.tx_data_12(tx_data_12),`	`.tx_data_12(tx_data_12),`
`/* End: Tx data registers */`	`/* End: Tx data registers */`

`/* Tx signal */`	`/* Tx signal */`
`.tx(tx_out),`	`.tx(tx_o),`
`.tx_oen(tx_oen)`	`.tx_oen(tx_oen_o)`

`ifdef CAN_BIST	`ifdef CAN_BIST
`,`	`,`
`/* BIST signals */`	`/* BIST signals */`
`.scanb_rst(scanb_rst),`	`.scanb_rst(scanb_rst),`
Line 688...	Line 692...
`.scanb_so(scanb_so),`	`.scanb_so(scanb_so),`
`.scanb_en(scanb_en)`	`.scanb_en(scanb_en)`
`endif	`endif
`);`	`);`

`assign tx_o = tx_oen? 1'bz : tx_out;`


`// Multiplexing wb_dat_o from registers and rx fifo`	`// Multiplexing wb_dat_o from registers and rx fifo`
`always @ (extended_mode or addr or reset_mode)`	`always @ (extended_mode or addr or reset_mode)`
`begin`	`begin`

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[/] [can/] [tags/] [rel_16/] [rtl/] [verilog/] [can_top.v] - Diff between revs 110 and 117