OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 95 and 100

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 95 Rev 100
Line 48... Line 48...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.35  2003/06/27 20:56:12  simons
 
// Virtual silicon ram instances added.
 
//
// Revision 1.34  2003/06/22 09:43:03  mohor
// Revision 1.34  2003/06/22 09:43:03  mohor
// synthesis full_case parallel_case fixed.
// synthesis full_case parallel_case fixed.
//
//
// Revision 1.33  2003/06/21 12:16:30  mohor
// Revision 1.33  2003/06/21 12:16:30  mohor
// paralel_case and full_case compiler directives added to case statements.
// paralel_case and full_case compiler directives added to case statements.
Line 224... Line 227...
  /* Clock Divider register */
  /* Clock Divider register */
  extended_mode,
  extended_mode,
 
 
  rx_idle,
  rx_idle,
  transmitting,
  transmitting,
 
  go_rx_inter,
  last_bit_of_inter,
  last_bit_of_inter,
  set_reset_mode,
  set_reset_mode,
  node_bus_off,
  node_bus_off,
  error_status,
  error_status,
  rx_err_cnt,
  rx_err_cnt,
Line 343... Line 347...
/* Tx Error Counter register */
/* Tx Error Counter register */
input         we_tx_err_cnt;
input         we_tx_err_cnt;
 
 
output        rx_idle;
output        rx_idle;
output        transmitting;
output        transmitting;
 
output        go_rx_inter;
output        last_bit_of_inter;
output        last_bit_of_inter;
output        set_reset_mode;
output        set_reset_mode;
output        node_bus_off;
output        node_bus_off;
output        error_status;
output        error_status;
output  [8:0] rx_err_cnt;
output  [8:0] rx_err_cnt;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.