| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.14 2003/01/16 13:36:19 mohor
|
|
// Form error supported. When receiving messages, last bit of the end-of-frame
|
|
// does not generate form error. Receiver goes to the idle mode one bit sooner.
|
|
// (CAN specification ver 2.0, part B, page 57).
|
|
//
|
// Revision 1.13 2003/01/15 21:59:45 mohor
|
// Revision 1.13 2003/01/15 21:59:45 mohor
|
// Data is stored to fifo at the end of ack stage.
|
// Data is stored to fifo at the end of ack stage.
|
//
|
//
|
// Revision 1.12 2003/01/15 21:05:11 mohor
|
// Revision 1.12 2003/01/15 21:05:11 mohor
|
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
|
// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
|
| Line 98... |
Line 103... |
rst,
|
rst,
|
|
|
sample_point,
|
sample_point,
|
sampled_bit,
|
sampled_bit,
|
sampled_bit_q,
|
sampled_bit_q,
|
|
tx_point,
|
hard_sync,
|
hard_sync,
|
resync,
|
|
|
|
addr,
|
addr,
|
data_out,
|
data_out,
|
|
|
|
|
| Line 116... |
Line 121... |
|
|
/* Clock Divider register */
|
/* Clock Divider register */
|
extended_mode,
|
extended_mode,
|
|
|
rx_idle,
|
rx_idle,
|
|
transmitting,
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
acceptance_code_0,
|
acceptance_code_0,
|
|
|
| Line 150... |
Line 156... |
tx_data_7,
|
tx_data_7,
|
tx_data_8,
|
tx_data_8,
|
tx_data_9,
|
tx_data_9,
|
tx_data_10,
|
tx_data_10,
|
tx_data_11,
|
tx_data_11,
|
tx_data_12
|
tx_data_12,
|
/* End: Tx data registers */
|
/* End: Tx data registers */
|
|
|
|
/* Tx signal */
|
|
tx
|
|
|
);
|
);
|
|
|
parameter Tp = 1;
|
parameter Tp = 1;
|
|
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input sample_point;
|
input sample_point;
|
input sampled_bit;
|
input sampled_bit;
|
input sampled_bit_q;
|
input sampled_bit_q;
|
|
input tx_point;
|
input hard_sync;
|
input hard_sync;
|
input resync;
|
|
input [7:0] addr;
|
input [7:0] addr;
|
output [7:0] data_out;
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output [7:0] data_out;
|
|
|
|
|
input reset_mode;
|
input reset_mode;
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| Line 176... |
Line 185... |
|
|
/* Command register */
|
/* Command register */
|
input release_buffer;
|
input release_buffer;
|
|
|
output rx_idle;
|
output rx_idle;
|
|
output transmitting;
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
/* This section is for BASIC and EXTENDED mode */
|
/* Acceptance code register */
|
/* Acceptance code register */
|
input [7:0] acceptance_code_0;
|
input [7:0] acceptance_code_0;
|
|
|
| Line 215... |
Line 225... |
input [7:0] tx_data_10;
|
input [7:0] tx_data_10;
|
input [7:0] tx_data_11;
|
input [7:0] tx_data_11;
|
input [7:0] tx_data_12;
|
input [7:0] tx_data_12;
|
/* End: Tx data registers */
|
/* End: Tx data registers */
|
|
|
|
/* Tx signal */
|
|
output tx;
|
|
|
reg reset_mode_q;
|
reg reset_mode_q;
|
reg [5:0] bit_cnt;
|
reg [5:0] bit_cnt;
|
|
|
reg [3:0] data_len;
|
reg [3:0] data_len;
|
| Line 243... |
Line 255... |
wire go_rx_crc;
|
wire go_rx_crc;
|
wire go_rx_crc_lim;
|
wire go_rx_crc_lim;
|
wire go_rx_ack;
|
wire go_rx_ack;
|
wire go_rx_ack_lim;
|
wire go_rx_ack_lim;
|
wire go_rx_eof;
|
wire go_rx_eof;
|
|
wire go_error_frame;
|
|
wire go_overload_frame;
|
|
wire go_rx_inter;
|
|
|
wire go_crc_enable;
|
wire go_crc_enable;
|
wire rst_crc_enable;
|
wire rst_crc_enable;
|
|
|
wire bit_de_stuff_set;
|
wire bit_de_stuff_set;
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| Line 265... |
Line 280... |
reg rx_crc;
|
reg rx_crc;
|
reg rx_crc_lim;
|
reg rx_crc_lim;
|
reg rx_ack;
|
reg rx_ack;
|
reg rx_ack_lim;
|
reg rx_ack_lim;
|
reg rx_eof;
|
reg rx_eof;
|
|
reg rx_inter;
|
|
|
reg rtr1;
|
reg rtr1;
|
reg ide;
|
reg ide;
|
reg rtr2;
|
reg rtr2;
|
reg [14:0] crc_in;
|
reg [14:0] crc_in;
|
|
|
|
reg [7:0] tmp_data;
|
|
reg [7:0] tmp_fifo [0:7];
|
|
reg write_data_to_tmp_fifo;
|
|
reg [2:0] byte_cnt;
|
|
reg bit_stuff_cnt_en;
|
reg crc_enable;
|
reg crc_enable;
|
|
|
reg [2:0] eof_cnt;
|
reg [2:0] eof_cnt;
|
wire [14:0] calculated_crc;
|
wire [14:0] calculated_crc;
|
wire remote_rq;
|
wire remote_rq;
|
wire [3:0] limited_data_len;
|
wire [3:0] limited_data_len;
|
reg form_error;
|
//reg form_error;
|
|
wire form_error;
|
wire set_form_error;
|
wire set_form_error;
|
|
reg transmitting;
|
|
|
|
reg error_frame;
|
|
reg enable_error_cnt2;
|
|
reg [2:0] error_cnt1;
|
|
reg [2:0] error_cnt2;
|
|
reg tx;
|
|
reg crc_error;
|
|
|
assign go_rx_idle = sample_point & rx_eof & (eof_cnt == 5); // Receiver ignores last (7th) bit of the end-of-frame.
|
wire error_frame_ended;
|
assign go_rx_id1 = sample_point & rx_idle & (~sampled_bit);
|
wire bit_error = 0; // FIX ME !!!
|
|
wire acknowledge_error = 0; // FIX ME !!!
|
|
wire need_to_tx = 0; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
|
|
// of intermission, it starts reading the identifier (and transmitting its own). // FIX ME !!!
|
|
wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
|
|
// be send in a row. Counter? FIX ME
|
|
|
|
assign go_rx_idle = sample_point & sampled_bit & rx_inter & (bit_cnt == 2); // Look the following line for TX
|
|
//assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2) & need_to_tx);
|
|
assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2));
|
assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);
|
assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);
|
assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;
|
assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;
|
assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;
|
assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;
|
assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);
|
assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);
|
assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;
|
assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;
|
| Line 296... |
Line 335... |
rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
|
rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
|
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt == 14);
|
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt == 14);
|
assign go_rx_ack = sample_point & rx_crc_lim;
|
assign go_rx_ack = sample_point & rx_crc_lim;
|
assign go_rx_ack_lim = sample_point & rx_ack;
|
assign go_rx_ack_lim = sample_point & rx_ack;
|
assign go_rx_eof = sample_point & rx_ack_lim | (~reset_mode) & reset_mode_q;
|
assign go_rx_eof = sample_point & rx_ack_lim | (~reset_mode) & reset_mode_q;
|
|
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended) & (~overload_needed);
|
|
|
|
assign go_error_frame = form_error | stuff_error | bit_error | acknowledge_error | (crc_error & go_rx_eof);
|
|
assign error_frame_ended = (error_cnt2 == 7) & tx_point;
|
|
|
|
assign go_overload_frame = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended) & overload_needed |
|
|
sample_point & (~sampled_bit) & rx_inter & ((bit_cnt == 0) | (bit_cnt == 1)) |
|
|
sample_point & (~sampled_bit) & (error_cnt2 == 7)
|
|
;
|
|
|
assign go_crc_enable = hard_sync;
|
assign go_crc_enable = hard_sync;
|
assign rst_crc_enable = go_rx_crc;
|
assign rst_crc_enable = go_rx_crc;
|
|
|
assign bit_de_stuff_set = go_rx_id1;
|
assign bit_de_stuff_set = go_rx_id1;
|
assign bit_de_stuff_reset = go_rx_crc_lim;
|
assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame;
|
|
|
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
|
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
|
|
|
|
|
// Rx idle state
|
// Rx idle state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_idle <= 1'b1;
|
rx_idle <= 1'b0;
|
else if (reset_mode | go_rx_id1)
|
else if (reset_mode | go_rx_id1 | error_frame)
|
rx_idle <=#Tp 1'b0;
|
rx_idle <=#Tp 1'b0;
|
else if (go_rx_idle)
|
else if (go_rx_idle)
|
rx_idle <=#Tp 1'b1;
|
rx_idle <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 324... |
Line 372... |
// Rx id1 state
|
// Rx id1 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_id1 <= 1'b0;
|
rx_id1 <= 1'b0;
|
else if (reset_mode | go_rx_rtr1)
|
else if (reset_mode | go_rx_rtr1 | error_frame)
|
rx_id1 <=#Tp 1'b0;
|
rx_id1 <=#Tp 1'b0;
|
else if (go_rx_id1)
|
else if (go_rx_id1)
|
rx_id1 <=#Tp 1'b1;
|
rx_id1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 336... |
Line 384... |
// Rx rtr1 state
|
// Rx rtr1 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_rtr1 <= 1'b0;
|
rx_rtr1 <= 1'b0;
|
else if (reset_mode | go_rx_ide)
|
else if (reset_mode | go_rx_ide | error_frame)
|
rx_rtr1 <=#Tp 1'b0;
|
rx_rtr1 <=#Tp 1'b0;
|
else if (go_rx_rtr1)
|
else if (go_rx_rtr1)
|
rx_rtr1 <=#Tp 1'b1;
|
rx_rtr1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 348... |
Line 396... |
// Rx ide state
|
// Rx ide state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ide <= 1'b0;
|
rx_ide <= 1'b0;
|
else if (reset_mode | go_rx_r0 | go_rx_id2)
|
else if (reset_mode | go_rx_r0 | go_rx_id2 | error_frame)
|
rx_ide <=#Tp 1'b0;
|
rx_ide <=#Tp 1'b0;
|
else if (go_rx_ide)
|
else if (go_rx_ide)
|
rx_ide <=#Tp 1'b1;
|
rx_ide <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 360... |
Line 408... |
// Rx id2 state
|
// Rx id2 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_id2 <= 1'b0;
|
rx_id2 <= 1'b0;
|
else if (reset_mode | go_rx_rtr2)
|
else if (reset_mode | go_rx_rtr2 | error_frame)
|
rx_id2 <=#Tp 1'b0;
|
rx_id2 <=#Tp 1'b0;
|
else if (go_rx_id2)
|
else if (go_rx_id2)
|
rx_id2 <=#Tp 1'b1;
|
rx_id2 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 372... |
Line 420... |
// Rx rtr2 state
|
// Rx rtr2 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_rtr2 <= 1'b0;
|
rx_rtr2 <= 1'b0;
|
else if (reset_mode | go_rx_r1)
|
else if (reset_mode | go_rx_r1 | error_frame)
|
rx_rtr2 <=#Tp 1'b0;
|
rx_rtr2 <=#Tp 1'b0;
|
else if (go_rx_rtr2)
|
else if (go_rx_rtr2)
|
rx_rtr2 <=#Tp 1'b1;
|
rx_rtr2 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 384... |
Line 432... |
// Rx r0 state
|
// Rx r0 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_r1 <= 1'b0;
|
rx_r1 <= 1'b0;
|
else if (reset_mode | go_rx_r0)
|
else if (reset_mode | go_rx_r0 | error_frame)
|
rx_r1 <=#Tp 1'b0;
|
rx_r1 <=#Tp 1'b0;
|
else if (go_rx_r1)
|
else if (go_rx_r1)
|
rx_r1 <=#Tp 1'b1;
|
rx_r1 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 396... |
Line 444... |
// Rx r0 state
|
// Rx r0 state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_r0 <= 1'b0;
|
rx_r0 <= 1'b0;
|
else if (reset_mode | go_rx_dlc)
|
else if (reset_mode | go_rx_dlc | error_frame)
|
rx_r0 <=#Tp 1'b0;
|
rx_r0 <=#Tp 1'b0;
|
else if (go_rx_r0)
|
else if (go_rx_r0)
|
rx_r0 <=#Tp 1'b1;
|
rx_r0 <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 408... |
Line 456... |
// Rx dlc state
|
// Rx dlc state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_dlc <= 1'b0;
|
rx_dlc <= 1'b0;
|
else if (reset_mode | go_rx_data | go_rx_crc)
|
else if (reset_mode | go_rx_data | go_rx_crc | error_frame)
|
rx_dlc <=#Tp 1'b0;
|
rx_dlc <=#Tp 1'b0;
|
else if (go_rx_dlc)
|
else if (go_rx_dlc)
|
rx_dlc <=#Tp 1'b1;
|
rx_dlc <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 420... |
Line 468... |
// Rx data state
|
// Rx data state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_data <= 1'b0;
|
rx_data <= 1'b0;
|
else if (reset_mode | go_rx_crc)
|
else if (reset_mode | go_rx_crc | error_frame)
|
rx_data <=#Tp 1'b0;
|
rx_data <=#Tp 1'b0;
|
else if (go_rx_data)
|
else if (go_rx_data)
|
rx_data <=#Tp 1'b1;
|
rx_data <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 432... |
Line 480... |
// Rx crc state
|
// Rx crc state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_crc <= 1'b0;
|
rx_crc <= 1'b0;
|
else if (reset_mode | go_rx_crc_lim)
|
else if (reset_mode | go_rx_crc_lim | error_frame)
|
rx_crc <=#Tp 1'b0;
|
rx_crc <=#Tp 1'b0;
|
else if (go_rx_crc)
|
else if (go_rx_crc)
|
rx_crc <=#Tp 1'b1;
|
rx_crc <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 444... |
Line 492... |
// Rx crc delimiter state
|
// Rx crc delimiter state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_crc_lim <= 1'b0;
|
rx_crc_lim <= 1'b0;
|
else if (reset_mode | go_rx_ack)
|
else if (reset_mode | go_rx_ack | error_frame)
|
rx_crc_lim <=#Tp 1'b0;
|
rx_crc_lim <=#Tp 1'b0;
|
else if (go_rx_crc_lim)
|
else if (go_rx_crc_lim)
|
rx_crc_lim <=#Tp 1'b1;
|
rx_crc_lim <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 456... |
Line 504... |
// Rx ack state
|
// Rx ack state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ack <= 1'b0;
|
rx_ack <= 1'b0;
|
else if (reset_mode | go_rx_ack_lim)
|
else if (reset_mode | go_rx_ack_lim | error_frame)
|
rx_ack <=#Tp 1'b0;
|
rx_ack <=#Tp 1'b0;
|
else if (go_rx_ack)
|
else if (go_rx_ack)
|
rx_ack <=#Tp 1'b1;
|
rx_ack <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 468... |
Line 516... |
// Rx ack delimiter state
|
// Rx ack delimiter state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_ack_lim <= 1'b0;
|
rx_ack_lim <= 1'b0;
|
else if (reset_mode | go_rx_eof)
|
else if (reset_mode | go_rx_eof | error_frame)
|
rx_ack_lim <=#Tp 1'b0;
|
rx_ack_lim <=#Tp 1'b0;
|
else if (go_rx_ack_lim)
|
else if (go_rx_ack_lim)
|
rx_ack_lim <=#Tp 1'b1;
|
rx_ack_lim <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 480... |
Line 528... |
// Rx eof state
|
// Rx eof state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_eof <= 1'b0;
|
rx_eof <= 1'b0;
|
else if (go_rx_idle)
|
else if (go_rx_inter | error_frame)
|
rx_eof <=#Tp 1'b0;
|
rx_eof <=#Tp 1'b0;
|
else if (go_rx_eof)
|
else if (go_rx_eof)
|
rx_eof <=#Tp 1'b1;
|
rx_eof <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
|
|
|
// Interframe space
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
rx_inter <= 1'b0;
|
|
else if (go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
|
|
rx_inter <=#Tp 1'b0;
|
|
else if (go_rx_inter)
|
|
rx_inter <=#Tp 1'b1;
|
|
end
|
|
|
|
|
// ID register
|
// ID register
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
id <= 0;
|
id <= 0;
|
| Line 538... |
Line 599... |
data_len <=#Tp {data_len[2:0], sampled_bit};
|
data_len <=#Tp {data_len[2:0], sampled_bit};
|
end
|
end
|
|
|
|
|
// Data
|
// Data
|
reg [7:0] tmp_data;
|
|
reg [7:0] tmp_fifo [0:7];
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tmp_data <= 0;
|
tmp_data <= 0;
|
else if (sample_point & rx_data & (~bit_de_stuff))
|
else if (sample_point & rx_data & (~bit_de_stuff))
|
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
end
|
end
|
|
|
|
|
reg write_data_to_tmp_fifo;
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
write_data_to_tmp_fifo <= 0;
|
write_data_to_tmp_fifo <= 0;
|
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
| Line 561... |
Line 619... |
else
|
else
|
write_data_to_tmp_fifo <=#Tp 0;
|
write_data_to_tmp_fifo <=#Tp 0;
|
end
|
end
|
|
|
|
|
reg [2:0] byte_cnt;
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
byte_cnt <= 0;
|
byte_cnt <= 0;
|
else if (write_data_to_tmp_fifo)
|
else if (write_data_to_tmp_fifo)
|
| Line 573... |
Line 630... |
else if (sample_point & go_rx_crc_lim)
|
else if (sample_point & go_rx_crc_lim)
|
byte_cnt <=#Tp 0;
|
byte_cnt <=#Tp 0;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk)
|
begin
|
begin
|
if (write_data_to_tmp_fifo)
|
if (write_data_to_tmp_fifo)
|
tmp_fifo[byte_cnt] <=#Tp tmp_data;
|
tmp_fifo[byte_cnt] <=#Tp tmp_data;
|
end
|
end
|
|
|
| Line 596... |
Line 653... |
// bit_cnt
|
// bit_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_cnt <= 0;
|
bit_cnt <= 0;
|
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc | go_rx_ack | go_rx_eof)
|
else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
|
|
go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
|
bit_cnt <=#Tp 0;
|
bit_cnt <=#Tp 0;
|
else if (sample_point & (~bit_de_stuff))
|
else if (sample_point & (~bit_de_stuff))
|
bit_cnt <=#Tp bit_cnt + 1'b1;
|
bit_cnt <=#Tp bit_cnt + 1'b1;
|
end
|
end
|
|
|
| Line 619... |
Line 677... |
end
|
end
|
end
|
end
|
|
|
|
|
// Enabling bit de-stuffing
|
// Enabling bit de-stuffing
|
reg bit_stuff_cnt_en;
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt_en <= 1'b0;
|
bit_stuff_cnt_en <= 1'b0;
|
else if (bit_de_stuff_set)
|
else if (bit_de_stuff_set)
|
bit_stuff_cnt_en <=#Tp 1'b1;
|
bit_stuff_cnt_en <=#Tp 1'b1;
|
else if (bit_de_stuff_reset)
|
else if (bit_de_stuff_reset)
|
bit_stuff_cnt_en <=#Tp 1'b0;
|
bit_stuff_cnt_en <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
// bit_stuff_cnt
|
// bit_stuff_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_stuff_cnt <= 1;
|
bit_stuff_cnt <= 1;
|
| Line 652... |
Line 710... |
|
|
|
|
assign bit_de_stuff = bit_stuff_cnt == 5;
|
assign bit_de_stuff = bit_stuff_cnt == 5;
|
|
|
|
|
|
|
// stuff_error
|
// stuff_error
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
stuff_error <= 0;
|
stuff_error <= 0;
|
else if (sample_point & (rx_id1) & bit_de_stuff & (sampled_bit == sampled_bit_q)) // Add other stages (data, control, etc.) !!!
|
else if (reset_mode | go_rx_idle | error_frame) // Stuff error might reset itself
|
|
stuff_error <=#Tp 0;
|
|
else if (sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q))
|
stuff_error <=#Tp 1'b1;
|
stuff_error <=#Tp 1'b1;
|
// else if (reset condition) // Add reset condition
|
|
// stuff_error <=#Tp 0;
|
|
end
|
end
|
|
|
|
|
// Generating delayed reset_mode signal
|
// Generating delayed reset_mode signal
|
always @ (posedge clk)
|
always @ (posedge clk)
|
| Line 683... |
Line 742... |
else if (reset_mode | rst_crc_enable)
|
else if (reset_mode | rst_crc_enable)
|
crc_enable <=#Tp 1'b0;
|
crc_enable <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
reg crc_error;
|
|
// CRC error generation
|
// CRC error generation
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
crc_error <= 0;
|
crc_error <= 0;
|
else if (go_rx_ack)
|
else if (go_rx_ack)
|
crc_error <=#Tp crc_in != calculated_crc;
|
crc_error <=#Tp crc_in != calculated_crc;
|
else if (reset_mode | rx_eof)
|
else if (reset_mode | go_rx_idle | error_frame) // CRC error might reset itself
|
crc_error <=#Tp 0;
|
crc_error <=#Tp 0;
|
end
|
end
|
|
|
|
|
// Conditions for form error
|
// Conditions for form error
|
assign set_form_error = sample_point & ( (~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) |
|
//assign set_form_error = sample_point & ( (~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) |
|
|
assign form_error = sample_point & ( (~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) |
|
rx_crc_lim & (~sampled_bit) |
|
rx_crc_lim & (~sampled_bit) |
|
rx_ack_lim & (~sampled_bit) |
|
rx_ack_lim & (~sampled_bit) |
|
rx_eof & (~sampled_bit)
|
rx_eof & (~sampled_bit)
|
);
|
);
|
|
|
|
/*
|
// Form error
|
// Form error
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
form_error <= 1'b0;
|
form_error <= 1'b0;
|
else if (reset_mode | form_error)
|
else if (reset_mode | go_rx_idle | error_frame)
|
form_error <=#Tp 1'b0;
|
form_error <=#Tp 1'b0;
|
else if (set_form_error)
|
else if (set_form_error)
|
form_error <=#Tp 1'b1;
|
form_error <=#Tp 1'b1;
|
end
|
end
|
|
*/
|
|
|
// Instantiation of the RX CRC module
|
// Instantiation of the RX CRC module
|
can_crc i_can_crc_rx
|
can_crc i_can_crc_rx
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
| Line 770... |
Line 829... |
.acceptance_mask_1(acceptance_mask_1),
|
.acceptance_mask_1(acceptance_mask_1),
|
.acceptance_mask_2(acceptance_mask_2),
|
.acceptance_mask_2(acceptance_mask_2),
|
.acceptance_mask_3(acceptance_mask_3),
|
.acceptance_mask_3(acceptance_mask_3),
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
.sample_point(sample_point),
|
|
.go_rx_crc_lim(go_rx_crc_lim),
|
.go_rx_crc_lim(go_rx_crc_lim),
|
.go_rx_idle(go_rx_idle),
|
.go_rx_idle(go_rx_idle),
|
|
|
.data0(tmp_fifo[0]),
|
.data0(tmp_fifo[0]),
|
.data1(tmp_fifo[1]),
|
.data1(tmp_fifo[1]),
|
| Line 799... |
Line 857... |
wire [2:0] header_len;
|
wire [2:0] header_len;
|
wire storing_header;
|
wire storing_header;
|
wire [3:0] limited_data_len_minus1;
|
wire [3:0] limited_data_len_minus1;
|
wire reset_wr_fifo;
|
wire reset_wr_fifo;
|
wire no_error;
|
wire no_error;
|
|
|
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
|
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
|
assign storing_header = header_cnt < header_len;
|
assign storing_header = header_cnt < header_len;
|
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
|
assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
|
assign reset_wr_fifo = data_cnt == (limited_data_len_minus1 + header_len);
|
assign reset_wr_fifo = data_cnt == (limited_data_len_minus1 + header_len);
|
assign no_error = ~crc_error;
|
assign no_error = (~crc_error) & (~form_error) & (~stuff_error);
|
|
|
|
|
|
|
// Write enable signal for 64-byte rx fifo
|
// Write enable signal for 64-byte rx fifo
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
wr_fifo <= 1'b0;
|
wr_fifo <= 1'b0;
|
else if (reset_wr_fifo)
|
else if (reset_wr_fifo)
|
wr_fifo <=#Tp 1'b0;
|
wr_fifo <=#Tp 1'b0;
|
else if (go_rx_idle & id_ok & no_error)
|
else if (go_rx_inter & id_ok & (~error_frame_ended))
|
wr_fifo <=#Tp 1'b1;
|
wr_fifo <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Header counter. Header length depends on the mode of operation and frame format.
|
// Header counter. Header length depends on the mode of operation and frame format.
|
| Line 842... |
Line 903... |
data_cnt <=#Tp data_cnt + 1;
|
data_cnt <=#Tp data_cnt + 1;
|
end
|
end
|
|
|
|
|
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
|
// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
|
always @ (extended_mode or ide or data_cnt or header_cnt or storing_header or id or rtr1 or rtr2 or data_len or
|
always @ (extended_mode or ide or data_cnt or header_cnt or header_len or
|
|
storing_header or id or rtr1 or rtr2 or data_len or
|
tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
|
tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
|
tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
|
tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
|
begin
|
begin
|
if (storing_header)
|
if (storing_header)
|
begin
|
begin
|
if (extended_mode) // extended mode
|
if (extended_mode) // extended mode
|
begin
|
begin
|
if (ide) // extended format
|
if (ide) // extended format
|
begin
|
begin
|
case (header_cnt) // synopsys parallel_case synopsys full_case
|
case (header_cnt) // synthesis parallel_case
|
4'h0 : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
|
3'h0 : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len};
|
4'h1 : data_for_fifo <= id[28:21];
|
3'h1 : data_for_fifo <= id[28:21];
|
4'h2 : data_for_fifo <= id[20:13];
|
3'h2 : data_for_fifo <= id[20:13];
|
4'h3 : data_for_fifo <= id[12:5];
|
3'h3 : data_for_fifo <= id[12:5];
|
4'h4 : data_for_fifo <= {id[4:0], 3'h0};
|
3'h4 : data_for_fifo <= {id[4:0], 3'h0};
|
|
default: data_for_fifo <= 0;
|
endcase
|
endcase
|
end
|
end
|
else // standard format
|
else // standard format
|
begin
|
begin
|
case (header_cnt) // synopsys parallel_case synopsys full_case
|
case (header_cnt) // synthesis parallel_case
|
4'h0 : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
|
3'h0 : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len};
|
4'h1 : data_for_fifo <= id[10:3];
|
3'h1 : data_for_fifo <= id[10:3];
|
4'h2 : data_for_fifo <= {id[2:0], 5'h0};
|
3'h2 : data_for_fifo <= {id[2:0], 5'h0};
|
|
default: data_for_fifo <= 0;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
else // normal mode
|
else // normal mode
|
begin
|
begin
|
case (header_cnt) // synopsys parallel_case synopsys full_case
|
case (header_cnt) // synthesis parallel_case
|
4'h0 : data_for_fifo <= id[10:3];
|
3'h0 : data_for_fifo <= id[10:3];
|
4'h1 : data_for_fifo <= {id[2:0], rtr1, data_len};
|
3'h1 : data_for_fifo <= {id[2:0], rtr1, data_len};
|
|
default: data_for_fifo <= 0;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
else
|
else
|
data_for_fifo <= tmp_fifo[data_cnt-header_len];
|
data_for_fifo <= tmp_fifo[data_cnt-header_len];
|
| Line 905... |
Line 970... |
|
|
);
|
);
|
|
|
|
|
|
|
|
// transmitting signals that core is a transmitter. No synchronization is done meanwhile.
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
transmitting <= 1'b0;
|
|
else if (go_rx_idle | reset_mode)
|
|
transmitting <=#Tp 1'b0;
|
|
else if (~no_error)
|
|
transmitting <=#Tp 1'b1;
|
|
end
|
|
|
|
|
|
|
|
// Transmitting error frame. The same counters are used for sending overload frame, too.
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
error_frame <= 1'b0;
|
|
else if (reset_mode | error_frame_ended)
|
|
error_frame <=#Tp 1'b0;
|
|
else if (go_error_frame | go_overload_frame)
|
|
error_frame <=#Tp 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
error_cnt1 <= 1'b0;
|
|
else if (reset_mode | error_frame_ended)
|
|
error_cnt1 <=#Tp 1'b0;
|
|
else if (error_frame & tx_point & (error_cnt1 < 6))
|
|
error_cnt1 <=#Tp error_cnt1 + 1'b1;
|
|
end
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
enable_error_cnt2 <= 1'b0;
|
|
else if (reset_mode | error_frame_ended)
|
|
enable_error_cnt2 <=#Tp 1'b0;
|
|
else if (sample_point & sampled_bit & (error_cnt1 == 6))
|
|
enable_error_cnt2 <=#Tp 1'b1;
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
error_cnt2 <= 1'b0;
|
|
else if (reset_mode | error_frame_ended)
|
|
error_cnt2 <=#Tp 1'b0;
|
|
else if (enable_error_cnt2 & tx_point)
|
|
error_cnt2 <=#Tp error_cnt2 + 1'b1;
|
|
end
|
|
|
|
|
|
wire node_error_passive = 1;
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
tx <= 1'b1;
|
|
else if (reset_mode | error_frame_ended)
|
|
tx <=#Tp 1'b1;
|
|
else if (tx_point & error_frame)
|
|
begin
|
|
if (error_cnt1 < 6)
|
|
begin
|
|
if (node_error_passive)
|
|
tx <=#Tp 1'b1;
|
|
else
|
|
tx <=#Tp 1'b0;
|
|
end
|
|
else if (error_cnt2 < 7)
|
|
tx <=#Tp 1'b1;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
