| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2003/02/11 00:56:06 mohor
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// Wishbone interface added.
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//
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// Revision 1.20 2003/02/10 16:02:11 mohor
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// Revision 1.20 2003/02/10 16:02:11 mohor
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// CAN is working according to the specification. WB interface and more
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// CAN is working according to the specification. WB interface and more
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// registers (status, IRQ, ...) needs to be added.
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// registers (status, IRQ, ...) needs to be added.
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//
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//
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// Revision 1.19 2003/02/09 18:40:29 mohor
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// Revision 1.19 2003/02/09 18:40:29 mohor
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| Line 147... |
Line 150... |
acceptance_filter_mode,
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acceptance_filter_mode,
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/* Command register */
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/* Command register */
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release_buffer,
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release_buffer,
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tx_request,
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tx_request,
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abort_tx,
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/* Clock Divider register */
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/* Clock Divider register */
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extended_mode,
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extended_mode,
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rx_idle,
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rx_idle,
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| Line 217... |
Line 221... |
input extended_mode;
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input extended_mode;
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/* Command register */
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/* Command register */
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input release_buffer;
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input release_buffer;
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input tx_request;
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input tx_request;
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input abort_tx;
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output rx_idle;
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output rx_idle;
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output transmitting;
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output transmitting;
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output last_bit_of_inter;
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output last_bit_of_inter;
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| Line 486... |
Line 491... |
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assign go_crc_enable = hard_sync | go_tx;
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assign go_crc_enable = hard_sync | go_tx;
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assign rst_crc_enable = go_rx_crc;
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assign rst_crc_enable = go_rx_crc;
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assign bit_de_stuff_set = go_rx_id1;
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assign bit_de_stuff_set = go_rx_id1 & (~go_error_frame);
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assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame | go_overload_frame;
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assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame | go_overload_frame;
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assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
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assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
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assign limited_data_len = (data_len < 8)? data_len : 4'h8;
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assign limited_data_len = (data_len < 8)? data_len : 4'h8;
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| Line 1110... |
Line 1115... |
begin
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begin
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if (rst)
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if (rst)
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wr_fifo <= 1'b0;
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wr_fifo <= 1'b0;
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else if (reset_wr_fifo)
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else if (reset_wr_fifo)
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wr_fifo <=#Tp 1'b0;
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wr_fifo <=#Tp 1'b0;
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// else if (go_rx_inter & id_ok & (~error_frame_ended)) // FIX ME !!! Look following line
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else if (go_rx_inter & id_ok & (~error_frame_ended)) // FIX ME !!! Look following line
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else if (go_rx_inter & id_ok & (~error_frame_ended) & (~tx_state)) // FIX ME !!! This line is the correct one. The above line is for easier debugging only.
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// else if (go_rx_inter & id_ok & (~error_frame_ended) & (~tx_state)) // FIX ME !!! This line is the correct one. The above line is for easier debugging only.
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wr_fifo <=#Tp 1'b1;
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wr_fifo <=#Tp 1'b1;
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end
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end
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// Header counter. Header length depends on the mode of operation and frame format.
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// Header counter. Header length depends on the mode of operation and frame format.
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| Line 1511... |
Line 1516... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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need_to_tx <= 1'b0;
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need_to_tx <= 1'b0;
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else if (tx_successful | node_bus_off)
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else if (tx_successful | node_bus_off | (abort_tx & (~transmitting)))
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need_to_tx <=#Tp 1'h0;
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need_to_tx <=#Tp 1'h0;
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else if (tx_request)
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else if (tx_request & sample_point)
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need_to_tx <=#Tp 1'b1;
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need_to_tx <=#Tp 1'b1;
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end
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end
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