OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_btl.v] - Diff between revs 29 and 35

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 29 Rev 35
Line 48... Line 48...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.11  2003/02/09 18:40:29  mohor
 
// Overload fixed. Hard synchronization also enabled at the last bit of
 
// interframe.
 
//
// Revision 1.10  2003/02/09 02:24:33  mohor
// Revision 1.10  2003/02/09 02:24:33  mohor
// Bosch license warning added. Error counters finished. Overload frames
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
// still need to be fixed.
//
//
// Revision 1.9  2003/01/31 01:13:38  mohor
// Revision 1.9  2003/01/31 01:13:38  mohor
Line 192... Line 196...
/* Generating general enable signal that defines baud rate. */
/* Generating general enable signal that defines baud rate. */
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    clk_cnt <= 0;
    clk_cnt <= 0;
  else if (clk_cnt == (preset_cnt-1) | reset_mode)
  else if (clk_cnt == (preset_cnt-1))
    clk_cnt <=#Tp 0;
    clk_cnt <=#Tp 0;
  else
  else
    clk_cnt <=#Tp clk_cnt + 1;
    clk_cnt <=#Tp clk_cnt + 1;
end
end
 
 
Line 275... Line 279...
/* Quant counter */
/* Quant counter */
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    quant_cnt <= 0;
    quant_cnt <= 0;
  else if (go_sync | go_seg1 | go_seg2 | reset_mode)
  else if (go_sync | go_seg1 | go_seg2)
    quant_cnt <=#Tp 0;
    quant_cnt <=#Tp 0;
  else if (clk_en)
  else if (clk_en)
    quant_cnt <=#Tp quant_cnt + 1'b1;
    quant_cnt <=#Tp quant_cnt + 1'b1;
end
end
 
 
Line 336... Line 340...
end
end
 
 
 
 
 
 
/* Blocking synchronization (can occur only once in a bit time) */
/* Blocking synchronization (can occur only once in a bit time) */
 
 
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
begin
begin
  if (rst)
  if (rst)
    sync_blocked <=#Tp 1'b0;
    sync_blocked <=#Tp 1'b0;
  else if (clk_en)
  else if (clk_en)
    begin
    begin
      if (hard_sync || resync)
      if (hard_sync | resync)
        sync_blocked <=#Tp 1'b1;
        sync_blocked <=#Tp 1'b1;
      else if (seg2 & quant_cnt == time_segment2)
      else if (seg2 & quant_cnt == time_segment2)
        sync_blocked <=#Tp 1'b0;
        sync_blocked <=#Tp 1'b0;
    end
    end
end
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.