| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.28 2003/07/07 11:21:37 mohor
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// Little fixes (to fix warnings).
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//
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// Revision 1.27 2003/06/22 09:43:03 mohor
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// Revision 1.27 2003/06/22 09:43:03 mohor
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// synthesi full_case parallel_case fixed.
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// synthesi full_case parallel_case fixed.
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//
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//
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// Revision 1.26 2003/06/22 01:33:14 mohor
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// Revision 1.26 2003/06/22 01:33:14 mohor
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// clkout is clk/2 after the reset.
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// clkout is clk/2 after the reset.
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| Line 186... |
Line 189... |
release_buffer,
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release_buffer,
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abort_tx,
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abort_tx,
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tx_request,
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tx_request,
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self_rx_request,
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self_rx_request,
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single_shot_transmission,
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single_shot_transmission,
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tx_state,
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tx_state_q,
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/* Arbitration Lost Capture Register */
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/* Arbitration Lost Capture Register */
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read_arbitration_lost_capture_reg,
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read_arbitration_lost_capture_reg,
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/* Error Code Capture Register */
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/* Error Code Capture Register */
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| Line 307... |
Line 312... |
output release_buffer;
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output release_buffer;
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output abort_tx;
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output abort_tx;
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output tx_request;
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output tx_request;
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output self_rx_request;
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output self_rx_request;
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output single_shot_transmission;
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output single_shot_transmission;
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input tx_state;
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input tx_state_q;
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/* Arbitration Lost Capture Register */
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/* Arbitration Lost Capture Register */
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output read_arbitration_lost_capture_reg;
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output read_arbitration_lost_capture_reg;
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/* Error Code Capture Register */
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/* Error Code Capture Register */
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| Line 391... |
Line 398... |
reg error_status_q;
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reg error_status_q;
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reg node_bus_off_q;
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reg node_bus_off_q;
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reg node_error_passive_q;
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reg node_error_passive_q;
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reg transmit_buffer_status;
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reg transmit_buffer_status;
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reg single_shot_transmission;
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reg single_shot_transmission;
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reg self_rx_request;
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// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
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// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
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wire data_overrun_irq_en;
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wire data_overrun_irq_en;
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wire error_warning_irq_en;
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wire error_warning_irq_en;
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| Line 514... |
Line 522... |
( .data_in(data_in[0]),
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( .data_in(data_in[0]),
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.data_out(command[0]),
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.data_out(command[0]),
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.we(we_command),
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.we(we_command),
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.rst_sync(tx_request & sample_point)
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.rst_sync(command[0] & sample_point)
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);
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);
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can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
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can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
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( .data_in(data_in[1]),
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( .data_in(data_in[1]),
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.data_out(command[1]),
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.data_out(command[1]),
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.we(we_command),
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.we(we_command),
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.rst_sync(abort_tx & ~transmitting)
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.rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)))
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);
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);
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can_register_asyn_syn #(2, 2'h0) COMMAND_REG
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can_register_asyn_syn #(2, 2'h0) COMMAND_REG
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( .data_in(data_in[3:2]),
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( .data_in(data_in[3:2]),
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.data_out(command[3:2]),
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.data_out(command[3:2]),
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| Line 541... |
Line 549... |
( .data_in(data_in[4]),
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( .data_in(data_in[4]),
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.data_out(command[4]),
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.data_out(command[4]),
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.we(we_command),
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.we(we_command),
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.rst_sync(tx_successful & (~tx_successful_q) | abort_tx)
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.rst_sync(command[4] & sample_point)
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);
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);
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assign self_rx_request = command[4] & (~command[0]);
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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self_rx_request <= 1'b0;
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else if (command[4] & (~command[0]))
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self_rx_request <=#Tp 1'b1;
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else if ((~tx_state) & tx_state_q)
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self_rx_request <=#Tp 1'b0;
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end
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assign clear_data_overrun = command[3];
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assign clear_data_overrun = command[3];
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assign release_buffer = command[2];
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assign release_buffer = command[2];
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assign abort_tx = command[1] & (~command[0]) & (~command[4]);
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assign tx_request = command[0] | command[4];
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assign tx_request = command[0] | command[4];
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assign abort_tx = command[1] & (~tx_request);
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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single_shot_transmission <= 1'b0;
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single_shot_transmission <= 1'b0;
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else if (we_command & data_in[1] & (data_in[1] | data_in[4]))
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else if (tx_request & command[1] & sample_point)
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single_shot_transmission <=#Tp 1'b1;
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single_shot_transmission <=#Tp 1'b1;
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else if (tx_successful & (~tx_successful_q))
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else if ((~tx_state) & tx_state_q)
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single_shot_transmission <=#Tp 1'b0;
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single_shot_transmission <=#Tp 1'b0;
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end
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end
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