OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_registers.v] - Diff between revs 125 and 141

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 125 Rev 141
Line 48... Line 48...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.31  2003/09/25 18:55:49  mohor
 
// Synchronization changed, error counters fixed.
 
//
// Revision 1.30  2003/07/16 15:19:34  mohor
// Revision 1.30  2003/07/16 15:19:34  mohor
// Fixed according to the linter.
// Fixed according to the linter.
// Case statement for data_out joined.
// Case statement for data_out joined.
//
//
// Revision 1.29  2003/07/10 01:59:04  tadejm
// Revision 1.29  2003/07/10 01:59:04  tadejm
Line 757... Line 760...
wire         clock_off;
wire         clock_off;
wire   [2:0] cd;
wire   [2:0] cd;
reg    [2:0] clkout_div;
reg    [2:0] clkout_div;
reg    [2:0] clkout_cnt;
reg    [2:0] clkout_cnt;
reg          clkout_tmp;
reg          clkout_tmp;
//reg          clkout;
 
 
 
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_7
can_register_asyn #(1, 0) CLOCK_DIVIDER_REG_7
( .data_in(data_in[7]),
( .data_in(data_in[7]),
  .data_out(clock_divider[7]),
  .data_out(clock_divider[7]),
  .we(we_clock_divider_hi),
  .we(we_clock_divider_hi),
Line 828... Line 830...
  else if (clkout_cnt == clkout_div)
  else if (clkout_cnt == clkout_div)
    clkout_tmp <=#Tp ~clkout_tmp;
    clkout_tmp <=#Tp ~clkout_tmp;
end
end
 
 
 
 
/*
 
//always @ (cd or clk or clkout_tmp or clock_off)
 
always @ (cd or clkout_tmp or clock_off)
 
begin
 
  if (clock_off)
 
    clkout <=#Tp 1'b1;
 
//  else if (&cd)
 
//    clkout <=#Tp clk;
 
  else
 
    clkout <=#Tp clkout_tmp;
 
end
 
*/
 
assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
 
 
 
 
 
 
/* End Clock Divider register */
/* End Clock Divider register */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.