| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.24 2003/06/09 11:22:54 mohor
|
|
// data_out is already registered in the can_top.v file.
|
|
//
|
// Revision 1.23 2003/04/15 15:31:24 mohor
|
// Revision 1.23 2003/04/15 15:31:24 mohor
|
// Some features are supported in extended mode only (listen_only_mode...).
|
// Some features are supported in extended mode only (listen_only_mode...).
|
//
|
//
|
// Revision 1.22 2003/03/20 16:58:50 mohor
|
// Revision 1.22 2003/03/20 16:58:50 mohor
|
// unix.
|
// unix.
|
| Line 724... |
Line 727... |
|
|
|
|
|
|
always @ (cd)
|
always @ (cd)
|
begin
|
begin
|
case (cd) // synopsys_full_case synopsys_paralel_case
|
case (cd) /* synthesis full_case synthesis parallel_case */
|
3'b000 : clkout_div <= 0;
|
3'b000 : clkout_div <= 0;
|
3'b001 : clkout_div <= 1;
|
3'b001 : clkout_div <= 1;
|
3'b010 : clkout_div <= 2;
|
3'b010 : clkout_div <= 2;
|
3'b011 : clkout_div <= 3;
|
3'b011 : clkout_div <= 3;
|
3'b100 : clkout_div <= 4;
|
3'b100 : clkout_div <= 4;
|
| Line 1017... |
Line 1020... |
begin
|
begin
|
if(read) // read
|
if(read) // read
|
begin
|
begin
|
if (extended_mode) // EXTENDED mode (Different register map depends on mode)
|
if (extended_mode) // EXTENDED mode (Different register map depends on mode)
|
begin
|
begin
|
case(addr)
|
case(addr) /* synthesis full_case synthesis parallel_case */
|
8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
|
8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
|
8'd1 : data_out <= 8'h0;
|
8'd1 : data_out <= 8'h0;
|
8'd2 : data_out <= status;
|
8'd2 : data_out <= status;
|
8'd3 : data_out <= irq_reg;
|
8'd3 : data_out <= irq_reg;
|
8'd4 : data_out <= irq_en_ext;
|
8'd4 : data_out <= irq_en_ext;
|
| Line 1051... |
Line 1054... |
default: data_out <= 8'h0;
|
default: data_out <= 8'h0;
|
endcase
|
endcase
|
end
|
end
|
else // BASIC mode
|
else // BASIC mode
|
begin
|
begin
|
case(addr)
|
case(addr) /* synthesis full_case synthesis parallel_case */
|
8'd0 : data_out <= {3'b001, mode_basic[4:1], mode[0]};
|
8'd0 : data_out <= {3'b001, mode_basic[4:1], mode[0]};
|
8'd1 : data_out <= 8'hff;
|
8'd1 : data_out <= 8'hff;
|
8'd2 : data_out <= status;
|
8'd2 : data_out <= status;
|
8'd3 : data_out <= {4'hf, irq_reg[3:0]};
|
8'd3 : data_out <= {4'hf, irq_reg[3:0]};
|
8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
|
8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
|
