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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_top.v] - Diff between revs 126 and 130

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Rev 126	Rev 130
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.45 2003/09/30 00:55:13 mohor`
	`// Error counters fixed to be compatible with Bosch VHDL reference model.`
	`// Small synchronization changes.`
	`//`
`// Revision 1.44 2003/09/25 18:55:49 mohor`	`// Revision 1.44 2003/09/25 18:55:49 mohor`
`// Synchronization changed, error counters fixed.`	`// Synchronization changed, error counters fixed.`
`//`	`//`
`// Revision 1.43 2003/08/20 09:57:39 mohor`	`// Revision 1.43 2003/08/20 09:57:39 mohor`
`// Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need`	`// Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need`
Line 230...	Line 234...

`// Bist`	`// Bist`
`ifdef CAN_BIST	`ifdef CAN_BIST
`,`	`,`
`// debug chain signals`	`// debug chain signals`
`scanb_rst, // bist scan reset`	`mbist_si_i, // bist scan serial in`
`scanb_clk, // bist scan clock`	`mbist_so_o, // bist scan serial out`
`scanb_si, // bist scan serial in`	`mbist_ctrl_i // bist chain shift control`
`scanb_so, // bist scan serial out`
`scanb_en // bist scan shift enable`
`endif	`endif
`);`	`);`

`parameter Tp = 1;`	`parameter Tp = 1;`

Line 285...	Line 287...
`output irq_on;`	`output irq_on;`
`output clkout_o;`	`output clkout_o;`

`// Bist`	`// Bist`
`ifdef CAN_BIST	`ifdef CAN_BIST
`input scanb_rst; // bist scan reset`	`input mbist_si_i; // bist scan serial in`
`input scanb_clk; // bist scan clock`	`output mbist_so_o; // bist scan serial out`
`input scanb_si; // bist scan serial in`	input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`output scanb_so; // bist scan serial out`
`input scanb_en; // bist scan shift enable`
`endif	`endif

`reg data_out_fifo_selected;`	`reg data_out_fifo_selected;`


Line 728...	Line 728...


`ifdef CAN_BIST	`ifdef CAN_BIST
`,`	`,`
`/* BIST signals */`	`/* BIST signals */`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_si_i),`
`.scanb_clk(scanb_clk),`	`.mbist_so_o(mbist_so_o),`
`.scanb_si(scanb_si),`	`.mbist_ctrl_i(mbist_ctrl_i)`
`.scanb_so(scanb_so),`
`.scanb_en(scanb_en)`
`endif	`endif
`);`	`);`

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_top.v] - Diff between revs 126 and 130