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//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.34  2003/06/13 15:02:24  mohor

// Revision 1.34  2003/06/13 15:02:24  mohor

// Synchronization is also needed when transmitting a message.

// Synchronization is also needed when transmitting a message.

//

//

// Revision 1.33  2003/06/11 14:21:35  mohor

// Revision 1.33  2003/06/11 14:21:35  mohor

// When switching to tx, sync stage is overjumped.

// When switching to tx, sync stage is overjumped.

    rst_i,

    rst_i,

    ale_i,

    ale_i,

    rd_i,

    rd_i,

    wr_i,

    wr_i,

    port_0_io,

    port_0_io,

  cs_can_i,

  cs_can_i,

  clk_i,

  clk_i,

  rx_i,

  rx_i,

  tx_o,

  tx_o,

  irq_on,

  irq_on,

  clkout_o

  clkout_o

`endif

`endif

);

);

parameter Tp = 1;

parameter Tp = 1;

`ifdef CAN_WISHBONE_IF

`ifdef CAN_WISHBONE_IF

  input        wb_clk_i;

  input        wb_clk_i;

  input        wb_rst_i;

  input        wb_rst_i;

  input  [7:0] wb_dat_i;

  input  [7:0] wb_dat_i;

  output [7:0] wb_dat_o;

  output [7:0] wb_dat_o;

  reg          cs_ack1;

  reg          cs_ack1;

  reg          cs_ack2;

  reg          cs_ack2;

  reg          cs_ack3;

  reg          cs_ack3;

  reg          cs_sync_rst1;

  reg          cs_sync_rst1;

  reg          cs_sync_rst2;

  reg          cs_sync_rst2;

`else

`else

  input        rst_i;

  input        rst_i;

  input        ale_i;

  input        ale_i;

  input        rd_i;

  input        rd_i;

  input        wr_i;

  input        wr_i;

  inout  [7:0] port_0_io;

  inout  [7:0] port_0_io;

  reg    [7:0] addr_latched;

  reg    [7:0] addr_latched;

  reg          wr_i_q;

  reg          wr_i_q;

  reg          rd_i_q;

  reg          rd_i_q;

`endif

`endif

input        clk_i;

input        clk_i;

input        rx_i;

input        rx_i;

output       tx_o;

output       tx_o;

output       irq_on;

output       irq_on;

output       clkout_o;

output       clkout_o;

wire         sample_point;

wire         sample_point;

wire         sampled_bit;

wire         sampled_bit;

wire         sampled_bit_q;

wire         sampled_bit_q;

wire         tx_point;

wire         tx_point;

wire         hard_sync;

wire         hard_sync;

/* output from can_bsp module */

/* output from can_bsp module */

wire         rx_idle;

wire         rx_idle;

wire         transmitting;

wire         transmitting;

wire         last_bit_of_inter;

wire         last_bit_of_inter;

wire         set_reset_mode;

wire         set_reset_mode;

wire         node_bus_off;

wire         node_bus_off;

wire         error_status;

wire         error_status;

wire   [7:0] rx_err_cnt;

wire   [7:0] rx_err_cnt;

  .sample_point(sample_point),

  .sample_point(sample_point),

  .sampled_bit(sampled_bit),

  .sampled_bit(sampled_bit),

  .sampled_bit_q(sampled_bit_q),

  .sampled_bit_q(sampled_bit_q),

  .tx_point(tx_point),

  .tx_point(tx_point),

  .hard_sync(hard_sync),

  .hard_sync(hard_sync),

  /* output from can_bsp module */

  /* output from can_bsp module */

  .rx_idle(rx_idle),

  .rx_idle(rx_idle),

  .last_bit_of_inter(last_bit_of_inter)

  .last_bit_of_inter(last_bit_of_inter)

);

);

  .sample_point(sample_point),

  .sample_point(sample_point),

  .sampled_bit(sampled_bit),

  .sampled_bit(sampled_bit),

  .sampled_bit_q(sampled_bit_q),

  .sampled_bit_q(sampled_bit_q),

  .tx_point(tx_point),

  .tx_point(tx_point),

  .hard_sync(hard_sync),

  .hard_sync(hard_sync),

  .addr(addr),

  .addr(addr),

  .data_in(data_in),

  .data_in(data_in),

  .data_out(data_out_fifo),

  .data_out(data_out_fifo),

  .fifo_selected(data_out_fifo_selected),

  .fifo_selected(data_out_fifo_selected),

  .extended_mode(extended_mode),

  .extended_mode(extended_mode),

  /* output from can_bsp module */

  /* output from can_bsp module */

  .rx_idle(rx_idle),

  .rx_idle(rx_idle),

  .transmitting(transmitting),

  .transmitting(transmitting),

  .last_bit_of_inter(last_bit_of_inter),

  .last_bit_of_inter(last_bit_of_inter),

  .set_reset_mode(set_reset_mode),

  .set_reset_mode(set_reset_mode),

  .node_bus_off(node_bus_off),

  .node_bus_off(node_bus_off),

  .error_status(error_status),

  .error_status(error_status),

  .rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}),   // The MSB is not displayed. It is just used for easier calculation (no counter overflow).

  .rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}),   // The MSB is not displayed. It is just used for easier calculation (no counter overflow).

end

end

`ifdef CAN_WISHBONE_IF

`ifdef CAN_WISHBONE_IF

  // Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain. 

  // Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain. 

  always @ (posedge clk_i or posedge rst)

  always @ (posedge clk_i or posedge rst)

  begin

  begin

    if (rst)

    if (rst)

      begin

      begin