| Line 155... |
Line 155... |
can_testbench.i_can_top.clk \
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can_testbench.i_can_top.clk \
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can_testbench.i_can_top.clk_en \
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can_testbench.i_can_top.clk_en \
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can_testbench.i_can_top.cs \
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can_testbench.i_can_top.cs \
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can_testbench.i_can_top.data_in[7:0]'h \
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can_testbench.i_can_top.data_in[7:0]'h \
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can_testbench.i_can_top.data_out[7:0]'h \
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can_testbench.i_can_top.data_out[7:0]'h \
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can_testbench.i_can_top.idle \
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can_testbench.i_can_top.listen_only_mode \
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can_testbench.i_can_top.listen_only_mode \
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can_testbench.i_can_top.reset_mode \
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can_testbench.i_can_top.reset_mode \
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can_testbench.i_can_top.rst \
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can_testbench.i_can_top.rst \
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can_testbench.i_can_top.rw \
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can_testbench.i_can_top.rw \
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can_testbench.i_can_top.rx \
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can_testbench.i_can_top.rx \
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can_testbench.i_can_top.sleep_mode \
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can_testbench.i_can_top.sleep_mode \
|
can_testbench.i_can_top.sync_jump_width[1:0]'h \
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can_testbench.i_can_top.sync_jump_width[1:0]'h \
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can_testbench.i_can_top.take_sample \
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|
can_testbench.i_can_top.time_segment1[3:0]'h \
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can_testbench.i_can_top.time_segment1[3:0]'h \
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can_testbench.i_can_top.time_segment2[2:0]'h \
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can_testbench.i_can_top.time_segment2[2:0]'h \
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can_testbench.i_can_top.triple_sampling \
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can_testbench.i_can_top.triple_sampling \
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add group \
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add group \
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can_btl \
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can_btl \
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can_testbench.i_can_top.i_can_btl.go_seg1 \
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can_testbench.i_can_top.i_can_btl.go_seg2 \
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can_testbench.i_can_top.i_can_btl.go_sync \
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can_testbench.i_can_top.i_can_btl.clk_cnt[8:0]'h \
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can_testbench.i_can_top.i_can_btl.clk_en \
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can_testbench.i_can_top.i_can_btl.quant_cnt[7:0]'h \
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can_testbench.i_can_top.i_can_btl.rx \
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can_testbench.i_can_top.i_can_btl.hard_sync \
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can_testbench.i_can_top.i_can_btl.hard_sync \
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can_testbench.i_can_top.i_can_btl.resync \
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can_testbench.i_can_top.i_can_btl.resync \
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can_testbench.i_can_top.i_can_btl.resync_latched \
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can_testbench.i_can_top.i_can_btl.rx \
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can_testbench.i_can_top.i_can_btl.sync_blocked \
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can_testbench.i_can_top.i_can_btl.sample_point \
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can_testbench.i_can_top.i_can_btl.sync \
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can_testbench.i_can_top.i_can_btl.seg1 \
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can_testbench.i_can_top.i_can_btl.seg2 \
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can_testbench.i_can_top.i_can_btl.sample_pulse \
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can_testbench.i_can_top.i_can_btl.sampled_bit \
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can_testbench.i_can_top.i_can_btl.sampled_bit \
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can_testbench.i_can_top.i_can_btl.sample[1:0]'h \
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|
add group \
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|
can_acf \
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can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_0[7:0]'h \
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can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_1[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_2[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_code_3[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_filter_mode \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_0[7:0]'h \
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|
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_1[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_2[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.acceptance_mask_3[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.clk \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.data0[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.data1[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.extended_mode \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.go_rx_crc_lim \
|
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can_testbench.i_can_top.i_can_bsp.i_can_acf.go_rx_idle \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.id[28:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.id_ok \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.ide \
|
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can_testbench.i_can_top.i_can_bsp.i_can_acf.match \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_df_ext \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_df_std \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_sf_ext \
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|
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_sf_std \
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|
can_testbench.i_can_top.i_can_bsp.i_can_acf.no_data \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.reset_mode \
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can_testbench.i_can_top.i_can_bsp.i_can_acf.rst \
|
|
can_testbench.i_can_top.i_can_bsp.i_can_acf.rtr1 \
|
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can_testbench.i_can_top.i_can_bsp.i_can_acf.rtr2 \
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can_testbench.i_can_top.i_can_bsp.i_can_acf.sample_point \
|
|
|
|
add group \
|
|
can_bsp \
|
|
can_testbench.i_can_top.i_can_bsp.bit_cnt[5:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.bit_de_stuff \
|
|
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_set \
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|
can_testbench.i_can_top.i_can_bsp.bit_de_stuff_reset \
|
|
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt_en \
|
|
can_testbench.i_can_top.i_can_bsp.bit_stuff_cnt[2:0]'h \
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|
can_testbench.i_can_top.i_can_bsp.byte_cnt[2:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.tmp_data[7:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.write_data_to_tmp_fifo \
|
|
can_testbench.i_can_top.i_can_bsp.calculated_crc[14:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.clk \
|
|
can_testbench.i_can_top.i_can_bsp.crc_enable \
|
|
can_testbench.i_can_top.i_can_bsp.crc_error \
|
|
can_testbench.i_can_top.i_can_bsp.crc_in[14:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.data_len[3:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.eof_cnt[2:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.go_crc_enable \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_ack \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_ack_lim \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_crc \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_crc_lim \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_data \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_dlc \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_eof \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_id1 \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_id2 \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_ide \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_idle \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_r0 \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_r1 \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_rtr1 \
|
|
can_testbench.i_can_top.i_can_bsp.go_rx_rtr2 \
|
|
can_testbench.i_can_top.i_can_bsp.id[28:0]'h \
|
|
can_testbench.i_can_top.i_can_bsp.ide \
|
|
can_testbench.i_can_top.i_can_bsp.reset_mode \
|
|
can_testbench.i_can_top.i_can_bsp.reset_mode_q \
|
|
can_testbench.i_can_top.i_can_bsp.rst \
|
|
can_testbench.i_can_top.i_can_btl.rx \
|
|
can_testbench.i_can_top.i_can_bsp.bit_de_stuff \
|
|
can_testbench.i_can_top.i_can_bsp.rst_crc_enable \
|
|
can_testbench.i_can_top.i_can_bsp.rtr1 \
|
|
can_testbench.i_can_top.i_can_bsp.rtr2 \
|
|
can_testbench.i_can_top.i_can_bsp.rx_ack \
|
|
can_testbench.i_can_top.i_can_bsp.rx_ack_lim \
|
|
can_testbench.i_can_top.i_can_bsp.rx_crc \
|
|
can_testbench.i_can_top.i_can_bsp.rx_crc_lim \
|
|
can_testbench.i_can_top.i_can_bsp.rx_data \
|
|
can_testbench.i_can_top.i_can_bsp.rx_dlc \
|
|
can_testbench.i_can_top.i_can_bsp.rx_eof \
|
|
can_testbench.i_can_top.i_can_bsp.rx_id1 \
|
|
can_testbench.i_can_top.i_can_bsp.rx_id2 \
|
|
can_testbench.i_can_top.i_can_bsp.rx_ide \
|
|
can_testbench.i_can_top.i_can_bsp.rx_idle \
|
|
can_testbench.i_can_top.i_can_bsp.rx_r0 \
|
|
can_testbench.i_can_top.i_can_bsp.rx_r1 \
|
|
can_testbench.i_can_top.i_can_bsp.rx_rtr1 \
|
|
can_testbench.i_can_top.i_can_bsp.rx_rtr2 \
|
|
can_testbench.i_can_top.i_can_bsp.sample_point \
|
|
can_testbench.i_can_top.i_can_bsp.sampled_bit \
|
|
can_testbench.i_can_top.i_can_bsp.sampled_bit_q \
|
|
can_testbench.i_can_top.i_can_bsp.stuff_error \
|
|
|
|
add group \
|
|
testbench \
|
|
can_testbench.send_frame.cnt's \
|
|
can_testbench.send_frame.crc[14:0]'h \
|
|
can_testbench.send_frame.data[28:0]'h \
|
|
can_testbench.send_frame.id[28:0]'h \
|
|
can_testbench.send_frame.len[3:0]'h \
|
|
can_testbench.send_frame.length[3:0]'h \
|
|
can_testbench.send_frame.mode \
|
|
|
|
add group \
|
|
rx_crc \
|
|
|
add group \
|
add group \
|
can_registers \
|
can_registers \
|
|
can_testbench.i_can_top.i_can_registers.acceptance_code_0[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.acceptance_code_1[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.acceptance_code_2[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.acceptance_code_3[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.acceptance_filter_mode \
|
can_testbench.i_can_top.i_can_registers.acceptance_filter_mode \
|
|
can_testbench.i_can_top.i_can_registers.acceptance_mask_0[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.acceptance_mask_1[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.acceptance_mask_2[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.acceptance_mask_3[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.addr[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.addr[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.baud_r_presc[5:0]'h \
|
can_testbench.i_can_top.i_can_registers.baud_r_presc[5:0]'h \
|
can_testbench.i_can_top.i_can_registers.bus_timing_0[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.bus_timing_0[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.bus_timing_1[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.bus_timing_1[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.cd[2:0]'h \
|
can_testbench.i_can_top.i_can_registers.clk \
|
can_testbench.i_can_top.i_can_registers.clk \
|
|
can_testbench.i_can_top.i_can_registers.clock_divider[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.clock_off \
|
can_testbench.i_can_top.i_can_registers.cs \
|
can_testbench.i_can_top.i_can_registers.cs \
|
can_testbench.i_can_top.i_can_registers.data_in[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.data_in[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.data_out[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.data_out[7:0]'h \
|
|
can_testbench.i_can_top.i_can_registers.extended_mode \
|
|
can_testbench.i_can_top.i_can_registers.fix_me[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.listen_only_mode \
|
can_testbench.i_can_top.i_can_registers.listen_only_mode \
|
can_testbench.i_can_top.i_can_registers.mode[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.mode[7:0]'h \
|
can_testbench.i_can_top.i_can_registers.read \
|
can_testbench.i_can_top.i_can_registers.read \
|
can_testbench.i_can_top.i_can_registers.reset_mode \
|
can_testbench.i_can_top.i_can_registers.reset_mode \
|
can_testbench.i_can_top.i_can_registers.rst \
|
can_testbench.i_can_top.i_can_registers.rst \
|
can_testbench.i_can_top.i_can_registers.rw \
|
can_testbench.i_can_top.i_can_registers.rw \
|
|
can_testbench.i_can_top.i_can_registers.rx_int_enable \
|
can_testbench.i_can_top.i_can_registers.sleep_mode \
|
can_testbench.i_can_top.i_can_registers.sleep_mode \
|
can_testbench.i_can_top.i_can_registers.sync_jump_width[1:0]'h \
|
can_testbench.i_can_top.i_can_registers.sync_jump_width[1:0]'h \
|
can_testbench.i_can_top.i_can_registers.time_segment1[3:0]'h \
|
can_testbench.i_can_top.i_can_registers.time_segment1[3:0]'h \
|
can_testbench.i_can_top.i_can_registers.time_segment2[2:0]'h \
|
can_testbench.i_can_top.i_can_registers.time_segment2[2:0]'h \
|
can_testbench.i_can_top.i_can_registers.triple_sampling \
|
can_testbench.i_can_top.i_can_registers.triple_sampling \
|
|
can_testbench.i_can_top.i_can_registers.we_acceptance_code_0 \
|
|
can_testbench.i_can_top.i_can_registers.we_acceptance_code_1 \
|
|
can_testbench.i_can_top.i_can_registers.we_acceptance_code_2 \
|
|
can_testbench.i_can_top.i_can_registers.we_acceptance_code_3 \
|
|
can_testbench.i_can_top.i_can_registers.we_acceptance_mask_0 \
|
|
can_testbench.i_can_top.i_can_registers.we_acceptance_mask_1 \
|
|
can_testbench.i_can_top.i_can_registers.we_acceptance_mask_2 \
|
|
can_testbench.i_can_top.i_can_registers.we_acceptance_mask_3 \
|
can_testbench.i_can_top.i_can_registers.we_bus_timing_0 \
|
can_testbench.i_can_top.i_can_registers.we_bus_timing_0 \
|
can_testbench.i_can_top.i_can_registers.we_bus_timing_1 \
|
can_testbench.i_can_top.i_can_registers.we_bus_timing_1 \
|
|
can_testbench.i_can_top.i_can_registers.we_clock_divider_hi \
|
|
can_testbench.i_can_top.i_can_registers.we_clock_divider_low \
|
can_testbench.i_can_top.i_can_registers.we_mode \
|
can_testbench.i_can_top.i_can_registers.we_mode \
|
|
|
|
|
deselect all
|
deselect all
|
open window waveform 1 geometry 10 59 1592 1140
|
open window waveform 1 geometry 10 59 1592 1140
|
zoom at 39711.18(0)ns 0.00144500 0.00000000
|
zoom at 58404.15(0)ns 0.00012325 0.00000000
|
zoom at 58404.15(0)ns 0.00012325 0.00000000
|
zoom at 58404.15(0)ns 0.00012325 0.00000000
|
