| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/12/28 04:13:53 mohor
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// Backup version.
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//
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// Revision 1.6 2002/12/27 00:12:48 mohor
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// Revision 1.6 2002/12/27 00:12:48 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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// Header changed, testbench improved to send a frame (crc still missing).
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//
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//
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// Revision 1.5 2002/12/26 16:00:29 mohor
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// Revision 1.5 2002/12/26 16:00:29 mohor
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// Testbench define file added. Clock divider register added.
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// Testbench define file added. Clock divider register added.
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| Line 88... |
Line 91... |
reg cs, rw;
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reg cs, rw;
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reg [7:0] addr;
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reg [7:0] addr;
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reg rx;
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reg rx;
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integer start_tb;
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integer start_tb;
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/* Instantiate can_top module */
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// Instantiate can_top module
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can_top i_can_top
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can_top i_can_top
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(
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(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.data_in(data_in),
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.data_in(data_in),
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| Line 128... |
Line 131... |
// Main testbench
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// Main testbench
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initial
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initial
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begin
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begin
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wait(start_tb);
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wait(start_tb);
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/* Set bus timing register 0 */
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// Set bus timing register 0
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write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
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write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
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/* Set bus timing register 1 */
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// Set bus timing register 1
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write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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// Set Clock Divider register
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write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
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// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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begin
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// Set Acceptance Code and Acceptance Mask registers
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write_register(8'h16, 8'ha6); // acceptance code 0
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write_register(8'h17, 8'hb0); // acceptance code 1
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write_register(8'h18, 8'h12); // acceptance code 2
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write_register(8'h19, 8'h34); // acceptance code 3
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write_register(8'h20, 8'h0); // acceptance mask 0
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write_register(8'h21, 8'h0); // acceptance mask 1
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write_register(8'h22, 8'h0); // acceptance mask 2
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write_register(8'h23, 8'h0); // acceptance mask 3
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end
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else
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begin
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// Set Acceptance Code and Acceptance Mask registers
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write_register(8'h4, 8'ha6); // acceptance code
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write_register(8'h5, 8'h00); // acceptance mask
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end
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#10;
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#10;
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repeat (1000) @ (posedge clk);
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repeat (1000) @ (posedge clk);
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/* Switch-off reset mode */
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// Switch-off reset mode
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write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
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write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
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repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
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repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
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// This difference is resynchronized later.
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// This difference is resynchronized later.
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repeat (7) send_bit(1); // Sending EOF
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// test_synchronization;
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// test_synchronization;
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repeat (7) send_bit(1); // Sending EOF
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send_frame(1, 29'h00075678, 1); // mode, id, length
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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begin
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send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
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// send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc
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end
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else
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begin
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send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
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end
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repeat (50000) @ (posedge clk);
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repeat (50000) @ (posedge clk);
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$display("CAN Testbench finished.");
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$display("CAN Testbench finished.");
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$stop;
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$stop;
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| Line 185... |
Line 219... |
task test_synchronization;
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task test_synchronization;
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begin
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begin
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// Hard synchronization
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// Hard synchronization
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#1 rx=0;
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#1 rx=0;
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repeat (2*BRP) @ (posedge clk);
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repeat (2*BRP) @ (posedge clk);
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// #1 idle = 0;
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repeat (8*BRP) @ (posedge clk);
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repeat (8*BRP) @ (posedge clk);
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#1 rx=1;
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#1 rx=1;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
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// Resynchronization on time
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// Resynchronization on time
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#1 rx=0;
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#1 rx=0;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
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#1 rx=1;
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#1 rx=1;
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// idle = 0;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
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// Resynchronization late
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// Resynchronization late
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repeat (BRP) @ (posedge clk);
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repeat (BRP) @ (posedge clk);
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repeat (BRP) @ (posedge clk);
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repeat (BRP) @ (posedge clk);
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#1 rx=0;
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#1 rx=0;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
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#1 rx=1;
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#1 rx=1;
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// idle = 0;
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// Resynchronization early
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// Resynchronization early
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repeat (8*BRP) @ (posedge clk); // two frames too early
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repeat (8*BRP) @ (posedge clk); // two frames too early
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#1 rx=0;
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#1 rx=0;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
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#1 rx=1;
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#1 rx=1;
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// idle = 0;
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
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end
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end
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endtask
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endtask
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Line 252... |
input bit;
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input bit;
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integer cnt;
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integer cnt;
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begin
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begin
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#1 rx=bit;
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#1 rx=bit;
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repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
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repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
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// idle=0;
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end
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end
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endtask
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endtask
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task send_frame;
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task send_frame;
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input mode;
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input mode;
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input remote_trans_req;
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input [28:0] id;
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input [28:0] id;
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input [3:0] length;
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input [3:0] length;
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input [14:0] crc;
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integer cnt;
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integer cnt;
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reg [28:0] data;
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reg [28:0] data;
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reg [3:0] len;
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reg [3:0] len;
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begin
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begin
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| Line 258... |
Line 289... |
begin
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begin
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send_bit(data[28]);
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send_bit(data[28]);
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data=data<<1;
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data=data<<1;
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end
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end
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send_bit(0); // RTR
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send_bit(remote_trans_req);
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send_bit(0); // r1 (reserved 1)
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send_bit(0); // r1 (reserved 1)
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send_bit(0); // r0 (reserved 0)
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send_bit(0); // r0 (reserved 0)
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for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
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for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
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begin
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begin
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| Line 275... |
Line 306... |
for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID
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for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID
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begin
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begin
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send_bit(data[10]);
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send_bit(data[10]);
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data=data<<1;
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data=data<<1;
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end
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end
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send_bit(0); // RTR
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send_bit(remote_trans_req);
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send_bit(0); // IDE
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send_bit(0); // IDE
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send_bit(0); // r0 (reserved 0)
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send_bit(0); // r0 (reserved 0)
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for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
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for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
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begin
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begin
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| Line 287... |
Line 318... |
len=len<<1;
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len=len<<1;
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end
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end
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end // End header
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end // End header
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for (cnt=0; cnt<(8*length); cnt=cnt+4) // data
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if(length) // Send data if length is > 0
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begin
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for (cnt=1; cnt<=(2*length); cnt=cnt+1) // data (we are sending nibbles)
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begin
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begin
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send_bit(cnt[3]);
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send_bit(cnt[3]);
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send_bit(cnt[2]);
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send_bit(cnt[2]);
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send_bit(cnt[1]);
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send_bit(cnt[1]);
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send_bit(cnt[0]);
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send_bit(cnt[0]);
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end
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end
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end
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// Send CRC
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data[14:0] = crc[14:0];
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for (cnt=0; cnt<15; cnt=cnt+1) // 15 bit CRC
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begin
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send_bit(data[14]);
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data=data<<1;
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end
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// Send CRC delimiter
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send_bit(1);
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// Send ACK slot
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send_bit(1);
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// Send Ack delimiter
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send_bit(1);
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// Nothing send after the data (just recessive bit)
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// Nothing send after the data (just recessive bit)
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send_bit(1);
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send_bit(1);
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| Line 305... |
Line 356... |
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end
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end
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endtask
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endtask
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/* State machine monitor (btl) */
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// State machine monitor (btl)
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
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if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
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can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
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can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
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begin
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begin
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