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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// can_testbench.v ////
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//// can_testbench.v ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocal Controller ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002 Authors ////
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//// Copyright (C) 2002, 2003 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/12/26 16:00:29 mohor
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// Testbench define file added. Clock divider register added.
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//
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// Revision 1.4 2002/12/26 01:33:01 mohor
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// Revision 1.4 2002/12/26 01:33:01 mohor
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// Tripple sampling supported.
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// Tripple sampling supported.
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//
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//
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// Revision 1.3 2002/12/25 23:44:12 mohor
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// Revision 1.3 2002/12/25 23:44:12 mohor
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// Commented lines removed.
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// Commented lines removed.
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write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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#10;
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#10;
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repeat (1000) @ (posedge clk);
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repeat (1000) @ (posedge clk);
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test_synchronization;
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// test_synchronization;
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// send_frame(mode, id, length);
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repeat (2) @ (posedge clk); // So we are not synchronized to anything
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send_frame(1, 29'h12345678, 1); // mode, id, length
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repeat (50000) @ (posedge clk);
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repeat (50000) @ (posedge clk);
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$display("CAN Testbench finished.");
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$display("CAN Testbench finished.");
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$stop;
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$stop;
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end
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end
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repeat (10*BRP) @ (posedge clk);
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repeat (10*BRP) @ (posedge clk);
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end
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end
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endtask
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endtask
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task send_bit;
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input bit;
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integer cnt;
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begin
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#1 rx=bit;
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repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
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idle=0;
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end
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endtask
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task send_frame;
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task send_frame;
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input mode;
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input mode;
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input id;
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input [28:0] id;
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input length;
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input [3:0] length;
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integer cnt;
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reg [28:0] data;
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reg [3:0] len;
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begin
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begin
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#1;
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data = id;
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len = length;
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send_bit(0); // SOF
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if(mode) // Extended format
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begin
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for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID
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begin
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send_bit(data[28]);
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data=data<<1;
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end
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send_bit(1); // SRR
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send_bit(1); // IDE
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for (cnt=11; cnt<29; cnt=cnt+1) // 18 bit ID
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begin
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send_bit(data[28]);
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data=data<<1;
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end
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send_bit(0); // RTR
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send_bit(0); // r1 (reserved 1)
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send_bit(0); // r0 (reserved 0)
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for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
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begin
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send_bit(len[3]);
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len=len<<1;
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end
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end
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else // Standard format
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begin
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for (cnt=0; cnt<11; cnt=cnt+1) // 11 bit ID
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begin
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send_bit(data[10]);
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data=data<<1;
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end
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send_bit(0); // RTR
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send_bit(0); // IDE
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send_bit(0); // r0 (reserved 0)
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for (cnt=0; cnt<4; cnt=cnt+1) // DLC (length)
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begin
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send_bit(len[3]);
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len=len<<1;
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end
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end // End header
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for (cnt=0; cnt<(8*length); cnt=cnt+4) // data
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begin
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send_bit(cnt[3]);
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send_bit(cnt[2]);
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send_bit(cnt[1]);
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send_bit(cnt[0]);
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end
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// Nothing send after the data (just recessive bit)
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send_bit(1);
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end
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end
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endtask
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endtask
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/* State machine monitor (btl) */
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/* State machine monitor (btl) */
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