| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.29 2003/07/10 01:59:04 tadejm
|
|
// Synchronization fixed. In some strange cases it didn't work according to
|
|
// the VHDL reference model.
|
|
//
|
// Revision 1.28 2003/07/07 11:21:37 mohor
|
// Revision 1.28 2003/07/07 11:21:37 mohor
|
// Little fixes (to fix warnings).
|
// Little fixes (to fix warnings).
|
//
|
//
|
// Revision 1.27 2003/06/22 09:43:03 mohor
|
// Revision 1.27 2003/06/22 09:43:03 mohor
|
// synthesi full_case parallel_case fixed.
|
// synthesi full_case parallel_case fixed.
|
| Line 392... |
Line 396... |
reg overrun_q;
|
reg overrun_q;
|
reg overrun_status;
|
reg overrun_status;
|
reg transmission_complete;
|
reg transmission_complete;
|
reg transmit_buffer_status_q;
|
reg transmit_buffer_status_q;
|
reg receive_buffer_status;
|
reg receive_buffer_status;
|
reg info_empty_q;
|
|
reg error_status_q;
|
reg error_status_q;
|
reg node_bus_off_q;
|
reg node_bus_off_q;
|
reg node_error_passive_q;
|
reg node_error_passive_q;
|
reg transmit_buffer_status;
|
reg transmit_buffer_status;
|
reg single_shot_transmission;
|
reg single_shot_transmission;
|
| Line 460... |
Line 463... |
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
tx_successful_q <=#Tp tx_successful;
|
tx_successful_q <=#Tp tx_successful;
|
overrun_q <=#Tp overrun;
|
overrun_q <=#Tp overrun;
|
transmit_buffer_status_q <=#Tp transmit_buffer_status;
|
transmit_buffer_status_q <=#Tp transmit_buffer_status;
|
info_empty_q <=#Tp info_empty;
|
|
error_status_q <=#Tp error_status;
|
error_status_q <=#Tp error_status;
|
node_bus_off_q <=#Tp node_bus_off;
|
node_bus_off_q <=#Tp node_bus_off;
|
node_error_passive_q <=#Tp node_error_passive;
|
node_error_passive_q <=#Tp node_error_passive;
|
end
|
end
|
|
|
| Line 759... |
Line 761... |
|
|
|
|
always @ (cd)
|
always @ (cd)
|
begin
|
begin
|
case (cd) /* synthesis full_case parallel_case */
|
case (cd) /* synthesis full_case parallel_case */
|
3'b000 : clkout_div <= 0;
|
3'b000 : clkout_div = 3'd0;
|
3'b001 : clkout_div <= 1;
|
3'b001 : clkout_div = 3'd1;
|
3'b010 : clkout_div <= 2;
|
3'b010 : clkout_div = 3'd2;
|
3'b011 : clkout_div <= 3;
|
3'b011 : clkout_div = 3'd3;
|
3'b100 : clkout_div <= 4;
|
3'b100 : clkout_div = 3'd4;
|
3'b101 : clkout_div <= 5;
|
3'b101 : clkout_div = 3'd5;
|
3'b110 : clkout_div <= 6;
|
3'b110 : clkout_div = 3'd6;
|
3'b111 : clkout_div <= 0;
|
3'b111 : clkout_div = 3'd0;
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
| Line 1038... |
Line 1040... |
|
|
|
|
|
|
|
|
// Reading data from registers
|
// Reading data from registers
|
always @ ( addr or read or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider or
|
always @ ( addr or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider or
|
acceptance_code_0 or acceptance_code_1 or acceptance_code_2 or acceptance_code_3 or
|
acceptance_code_0 or acceptance_code_1 or acceptance_code_2 or acceptance_code_3 or
|
acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or
|
acceptance_mask_0 or acceptance_mask_1 or acceptance_mask_2 or acceptance_mask_3 or
|
reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or
|
reset_mode or tx_data_0 or tx_data_1 or tx_data_2 or tx_data_3 or tx_data_4 or
|
tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or
|
tx_data_5 or tx_data_6 or tx_data_7 or tx_data_8 or tx_data_9 or status or
|
error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or
|
error_warning_limit or rx_err_cnt or tx_err_cnt or irq_en_ext or irq_reg or mode_ext or
|
arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code
|
arbitration_lost_capture or rx_message_counter or mode_basic or error_capture_code
|
)
|
)
|
begin
|
begin
|
if(read) // read
|
case({extended_mode, addr[4:0]}) /* synthesis parallel_case */
|
begin
|
{1'h1, 5'd00} : data_out = {4'b0000, mode_ext[3:1], mode[0]}; // extended mode
|
if (extended_mode) // EXTENDED mode (Different register map depends on mode)
|
{1'h1, 5'd01} : data_out = 8'h0; // extended mode
|
begin
|
{1'h1, 5'd02} : data_out = status; // extended mode
|
case(addr) /* synthesis full_case parallel_case */
|
{1'h1, 5'd03} : data_out = irq_reg; // extended mode
|
8'd0 : data_out <= {4'b0000, mode_ext[3:1], mode[0]};
|
{1'h1, 5'd04} : data_out = irq_en_ext; // extended mode
|
8'd1 : data_out <= 8'h0;
|
{1'h1, 5'd06} : data_out = bus_timing_0; // extended mode
|
8'd2 : data_out <= status;
|
{1'h1, 5'd07} : data_out = bus_timing_1; // extended mode
|
8'd3 : data_out <= irq_reg;
|
{1'h1, 5'd11} : data_out = {3'h0, arbitration_lost_capture[4:0]}; // extended mode
|
8'd4 : data_out <= irq_en_ext;
|
{1'h1, 5'd12} : data_out = error_capture_code; // extended mode
|
8'd6 : data_out <= bus_timing_0;
|
{1'h1, 5'd13} : data_out = error_warning_limit; // extended mode
|
8'd7 : data_out <= bus_timing_1;
|
{1'h1, 5'd14} : data_out = rx_err_cnt; // extended mode
|
8'd11 : data_out <= {3'h0, arbitration_lost_capture[4:0]};
|
{1'h1, 5'd15} : data_out = tx_err_cnt; // extended mode
|
8'd12 : data_out <= error_capture_code;
|
{1'h1, 5'd16} : data_out = acceptance_code_0; // extended mode
|
8'd13 : data_out <= error_warning_limit;
|
{1'h1, 5'd17} : data_out = acceptance_code_1; // extended mode
|
8'd14 : data_out <= rx_err_cnt;
|
{1'h1, 5'd18} : data_out = acceptance_code_2; // extended mode
|
8'd15 : data_out <= tx_err_cnt;
|
{1'h1, 5'd19} : data_out = acceptance_code_3; // extended mode
|
8'd16 : data_out <= acceptance_code_0;
|
{1'h1, 5'd20} : data_out = acceptance_mask_0; // extended mode
|
8'd17 : data_out <= acceptance_code_1;
|
{1'h1, 5'd21} : data_out = acceptance_mask_1; // extended mode
|
8'd18 : data_out <= acceptance_code_2;
|
{1'h1, 5'd22} : data_out = acceptance_mask_2; // extended mode
|
8'd19 : data_out <= acceptance_code_3;
|
{1'h1, 5'd23} : data_out = acceptance_mask_3; // extended mode
|
8'd20 : data_out <= acceptance_mask_0;
|
{1'h1, 5'd24} : data_out = 8'h0; // extended mode
|
8'd21 : data_out <= acceptance_mask_1;
|
{1'h1, 5'd25} : data_out = 8'h0; // extended mode
|
8'd22 : data_out <= acceptance_mask_2;
|
{1'h1, 5'd26} : data_out = 8'h0; // extended mode
|
8'd23 : data_out <= acceptance_mask_3;
|
{1'h1, 5'd27} : data_out = 8'h0; // extended mode
|
8'd24 : data_out <= 8'h0;
|
{1'h1, 5'd28} : data_out = 8'h0; // extended mode
|
8'd25 : data_out <= 8'h0;
|
{1'h1, 5'd29} : data_out = {1'b0, rx_message_counter}; // extended mode
|
8'd26 : data_out <= 8'h0;
|
{1'h1, 5'd31} : data_out = clock_divider; // extended mode
|
8'd27 : data_out <= 8'h0;
|
{1'h0, 5'd00} : data_out = {3'b001, mode_basic[4:1], mode[0]}; // basic mode
|
8'd28 : data_out <= 8'h0;
|
{1'h0, 5'd01} : data_out = 8'hff; // basic mode
|
8'd29 : data_out <= {1'b0, rx_message_counter};
|
{1'h0, 5'd02} : data_out = status; // basic mode
|
8'd31 : data_out <= clock_divider;
|
{1'h0, 5'd03} : data_out = {4'hf, irq_reg[3:0]}; // basic mode
|
|
{1'h0, 5'd04} : data_out = reset_mode? acceptance_code_0 : 8'hff; // basic mode
|
|
{1'h0, 5'd05} : data_out = reset_mode? acceptance_mask_0 : 8'hff; // basic mode
|
|
{1'h0, 5'd06} : data_out = reset_mode? bus_timing_0 : 8'hff; // basic mode
|
|
{1'h0, 5'd07} : data_out = reset_mode? bus_timing_1 : 8'hff; // basic mode
|
|
{1'h0, 5'd10} : data_out = reset_mode? 8'hff : tx_data_0; // basic mode
|
|
{1'h0, 5'd11} : data_out = reset_mode? 8'hff : tx_data_1; // basic mode
|
|
{1'h0, 5'd12} : data_out = reset_mode? 8'hff : tx_data_2; // basic mode
|
|
{1'h0, 5'd13} : data_out = reset_mode? 8'hff : tx_data_3; // basic mode
|
|
{1'h0, 5'd14} : data_out = reset_mode? 8'hff : tx_data_4; // basic mode
|
|
{1'h0, 5'd15} : data_out = reset_mode? 8'hff : tx_data_5; // basic mode
|
|
{1'h0, 5'd16} : data_out = reset_mode? 8'hff : tx_data_6; // basic mode
|
|
{1'h0, 5'd17} : data_out = reset_mode? 8'hff : tx_data_7; // basic mode
|
|
{1'h0, 5'd18} : data_out = reset_mode? 8'hff : tx_data_8; // basic mode
|
|
{1'h0, 5'd19} : data_out = reset_mode? 8'hff : tx_data_9; // basic mode
|
|
{1'h0, 5'd31} : data_out = clock_divider; // basic mode
|
|
default : data_out = 8'h0; // the rest is read as 0
|
endcase
|
endcase
|
end
|
end
|
else // BASIC mode
|
|
begin
|
|
case(addr) /* synthesis full_case parallel_case */
|
|
8'd0 : data_out <= {3'b001, mode_basic[4:1], mode[0]};
|
|
8'd1 : data_out <= 8'hff;
|
|
8'd2 : data_out <= status;
|
|
8'd3 : data_out <= {4'hf, irq_reg[3:0]};
|
|
8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
|
|
8'd5 : data_out <= reset_mode? acceptance_mask_0 : 8'hff;
|
|
8'd6 : data_out <= reset_mode? bus_timing_0 : 8'hff;
|
|
8'd7 : data_out <= reset_mode? bus_timing_1 : 8'hff;
|
|
8'd10 : data_out <= reset_mode? 8'hff : tx_data_0;
|
|
8'd11 : data_out <= reset_mode? 8'hff : tx_data_1;
|
|
8'd12 : data_out <= reset_mode? 8'hff : tx_data_2;
|
|
8'd13 : data_out <= reset_mode? 8'hff : tx_data_3;
|
|
8'd14 : data_out <= reset_mode? 8'hff : tx_data_4;
|
|
8'd15 : data_out <= reset_mode? 8'hff : tx_data_5;
|
|
8'd16 : data_out <= reset_mode? 8'hff : tx_data_6;
|
|
8'd17 : data_out <= reset_mode? 8'hff : tx_data_7;
|
|
8'd18 : data_out <= reset_mode? 8'hff : tx_data_8;
|
|
8'd19 : data_out <= reset_mode? 8'hff : tx_data_9;
|
|
8'd31 : data_out <= clock_divider;
|
|
endcase
|
|
end
|
|
end
|
|
else
|
|
data_out <= 8'h0;
|
|
end
|
|
|
|
|
|
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
assign data_overrun_irq_en = extended_mode ? data_overrun_irq_en_ext : overrun_irq_en_basic;
|
assign data_overrun_irq_en = extended_mode ? data_overrun_irq_en_ext : overrun_irq_en_basic;
|
assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;
|
assign error_warning_irq_en = extended_mode ? error_warning_irq_en_ext : error_irq_en_basic;
|
