URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_24/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 139 and 140

Rev 139	Rev 140
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.39 2004/03/18 17:15:26 igorm`
	`// Signal bus_off_on added.`
	`//`
`// Revision 1.38 2003/10/17 05:55:18 markom`	`// Revision 1.38 2003/10/17 05:55:18 markom`
`// mbist signals updated according to newest convention`	`// mbist signals updated according to newest convention`
`//`	`//`
`// Revision 1.37 2003/09/30 20:53:58 mohor`	`// Revision 1.37 2003/09/30 20:53:58 mohor`
`// Fixing the core to be Bosch VHDL Reference compatible.`	`// Fixing the core to be Bosch VHDL Reference compatible.`
Line 273...	Line 276...
`endif	`endif
`);`	`);`


`// Combining tx with the output enable signal.`	`// Combining tx with the output enable signal.`
`assign tx = tx_oen? 1'bz : tx_i;`	`assign tx = bus_off_on? tx_i : 1'bz;`

`ifdef CAN_WISHBONE_IF	`ifdef CAN_WISHBONE_IF
`// Generate wishbone clock signal 10 MHz`	`// Generate wishbone clock signal 10 MHz`
`initial`	`initial`
`begin`	`begin`