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[/] [can/] [tags/] [rel_24/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 139 and 140
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Rev 139 |
Rev 140 |
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Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.39 2004/03/18 17:15:26 igorm
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// Signal bus_off_on added.
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//
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// Revision 1.38 2003/10/17 05:55:18 markom
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// Revision 1.38 2003/10/17 05:55:18 markom
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// mbist signals updated according to newest convention
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// mbist signals updated according to newest convention
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//
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//
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// Revision 1.37 2003/09/30 20:53:58 mohor
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// Revision 1.37 2003/09/30 20:53:58 mohor
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// Fixing the core to be Bosch VHDL Reference compatible.
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// Fixing the core to be Bosch VHDL Reference compatible.
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Line 276... |
`endif
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`endif
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);
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);
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// Combining tx with the output enable signal.
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// Combining tx with the output enable signal.
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assign tx = tx_oen? 1'bz : tx_i;
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assign tx = bus_off_on? tx_i : 1'bz;
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`ifdef CAN_WISHBONE_IF
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`ifdef CAN_WISHBONE_IF
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// Generate wishbone clock signal 10 MHz
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// Generate wishbone clock signal 10 MHz
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initial
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initial
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begin
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begin
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