URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_24/] [bench/] [verilog/] [can_testbench_defines.v] - Diff between revs 10 and 11

Rev 10	Rev 11
Line 43...	Line 43...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2002/12/28 04:13:53 mohor`
	`// Backup version.`
	`//`
`// Revision 1.2 2002/12/27 00:12:48 mohor`	`// Revision 1.2 2002/12/27 00:12:48 mohor`
`// Header changed, testbench improved to send a frame (crc still missing).`	`// Header changed, testbench improved to send a frame (crc still missing).`
`//`	`//`
`// Revision 1.1 2002/12/26 16:00:29 mohor`	`// Revision 1.1 2002/12/26 16:00:29 mohor`
`// Testbench define file added. Clock divider register added.`	`// Testbench define file added. Clock divider register added.`
Line 65...	Line 68...
`// Bit Timing 1 register value`	`// Bit Timing 1 register value`
`define CAN_TIMING1_TSEG1 4'h4 // TSEG1 segment (value+1)	`define CAN_TIMING1_TSEG1 4'h4 // TSEG1 segment (value+1)
`define CAN_TIMING1_TSEG2 3'h3 // TSEG2 segment (value+1)	`define CAN_TIMING1_TSEG2 3'h3 // TSEG2 segment (value+1)
`define CAN_TIMING1_SAM 1'h0 // Triple sampling	`define CAN_TIMING1_SAM 1'h0 // Triple sampling

	`// Clock Divider register`
	`define CAN_CLOCK_DIVIDER_MODE 1'h1 // Normal (not extended mode

`No newline at end of file`	`No newline at end of file`