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[/] [can/] [tags/] [rel_24/] [rtl/] [verilog/] [can_crc.v] - Diff between revs 28 and 30

Rev 28	Rev 30
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2003/02/09 02:24:33 mohor`
	`// Bosch license warning added. Error counters finished. Overload frames`
	`// still need to be fixed.`
	`//`
`// Revision 1.1 2003/01/08 02:10:54 mohor`	`// Revision 1.1 2003/01/08 02:10:54 mohor`
`// Acceptance filter added.`	`// Acceptance filter added.`
`//`	`//`
`//`	`//`
`//`	`//`
Line 66...	Line 70...

`parameter Tp = 1;`	`parameter Tp = 1;`

`input clk;`	`input clk;`
`input data;`	`input data;`
`input enable; // Must be Destuffed !!!`	`input enable;`
`input initialize;`	`input initialize;`

`output [14:0] crc;`	`output [14:0] crc;`

`reg [14:0] crc;`	`reg [14:0] crc;`
Line 84...	Line 88...

`always @ (posedge clk)`	`always @ (posedge clk)`
`begin`	`begin`
`if(initialize)`	`if(initialize)`
`crc <= #Tp 0;`	`crc <= #Tp 0;`
`// else if (crc_next)`
`// crc <= #Tp {crc[13:0], 1'b0} ^ 15'h4599;`
`// else`
`// crc <= #Tp {crc[13:0], 1'b0};`
`else if (enable)`	`else if (enable)`
`begin`	`begin`
`if (crc_next)`	`if (crc_next)`
`crc <= #Tp crc_tmp ^ 15'h4599;`	`crc <= #Tp crc_tmp ^ 15'h4599;`
`else`	`else`