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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.16 2003/02/04 14:34:52 mohor
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// *** empty log message ***
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//
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// Revision 1.15 2003/01/31 01:13:37 mohor
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// Revision 1.15 2003/01/31 01:13:37 mohor
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// backup.
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// backup.
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//
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//
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// Revision 1.14 2003/01/16 13:36:19 mohor
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// Revision 1.14 2003/01/16 13:36:19 mohor
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// Form error supported. When receiving messages, last bit of the end-of-frame
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// Form error supported. When receiving messages, last bit of the end-of-frame
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| Line 325... |
Line 328... |
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reg priority_lost;
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reg priority_lost;
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reg tx_q;
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reg tx_q;
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wire error_frame_ended;
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wire error_frame_ended;
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wire bit_error = 0; // FIX ME !!!
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wire bit_error;
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wire acknowledge_error;
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wire acknowledge_error;
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reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
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reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
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// of intermission, it starts reading the identifier (and transmitting its own). // FIX ME !!!
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// of intermission, it starts reading the identifier (and transmitting its own).
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wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
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wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
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// be send in a row. Counter? FIX ME
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// be send in a row. This is not implemented because host can not send an overload request. FIX ME !!!!
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wire id_ok; // If received ID matches ID set in registers
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wire id_ok; // If received ID matches ID set in registers
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wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
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wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
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wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
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wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
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reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
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reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
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| Line 353... |
Line 356... |
wire reset_wr_fifo;
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wire reset_wr_fifo;
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wire no_error;
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wire no_error;
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assign go_rx_idle = sample_point & sampled_bit & rx_inter & (bit_cnt == 2); // Look the following line for TX
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assign go_rx_idle = sample_point & sampled_bit & rx_inter & (bit_cnt == 2); // Look the following line for TX
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//assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2) & need_to_tx);
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assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2));
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assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | rx_inter & (bit_cnt == 2));
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assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);
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assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt == 10);
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assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;
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assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;
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assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;
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assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;
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assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);
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assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt == 17);
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| Line 390... |
Line 392... |
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assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
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assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
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assign limited_data_len = (data_len < 8)? data_len : 4'h8;
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assign limited_data_len = (data_len < 8)? data_len : 4'h8;
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assign acknowledge_error = rx_ack & sample_point & sampled_bit & tx_state;
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assign acknowledge_error = rx_ack & sample_point & sampled_bit & tx_state;
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assign bit_error = tx_state & sample_point & tx & (~sampled_bit) & (~rx_ack) & (~rx_id1) & (~rx_rtr1) & (~rx_ide) & (~rx_id2) & (~rx_rtr2);
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// Rx idle state
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// Rx idle state
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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| Line 1000... |
Line 1004... |
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);
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);
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// transmitting signals that core is a transmitter. No synchronization is done meanwhile.
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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transmitting <= 1'b0;
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else if (go_rx_idle | reset_mode | priority_lost)
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transmitting <=#Tp 1'b0;
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else if (~no_error | go_tx)
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transmitting <=#Tp 1'b1;
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end
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// Transmitting error frame. The same counters are used for sending overload frame, too.
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// Transmitting error frame. The same counters are used for sending overload frame, too.
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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error_frame <= 1'b0;
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error_frame <= 1'b0;
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Line 1200... |
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
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else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
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tx_pointer <=#Tp tx_pointer + 1'b1;
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tx_pointer <=#Tp tx_pointer + 1'b1;
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end
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end
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wire rst_need_to_tx = go_rx_inter & (~error_frame & (~priority_lost)); // FIX ME !!! When there is no error until the end-of-frame, tx is ok (finished).
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wire rst_need_to_tx = go_rx_inter & (~error_frame) & (~priority_lost);
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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need_to_tx <= 1'b0;
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need_to_tx <= 1'b0;
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else if (rst_need_to_tx)
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else if (rst_need_to_tx)
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Line 1230... |
tx_state <=#Tp 1'b1;
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tx_state <=#Tp 1'b1;
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end
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end
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// transmitting signals that core is a transmitter. No synchronization is done meanwhile.
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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transmitting <= 1'b0;
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else if (go_rx_idle | reset_mode | priority_lost) // FIX ME !!! This line might not be ok.
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transmitting <=#Tp 1'b0;
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else if (~no_error | go_tx)
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transmitting <=#Tp 1'b1;
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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finish_msg <= 1'b0;
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finish_msg <= 1'b0;
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else if (go_rx_idle | error_frame | reset_mode)
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else if (go_rx_idle | error_frame | reset_mode)
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