| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.19 2003/02/09 18:40:29 mohor
|
|
// Overload fixed. Hard synchronization also enabled at the last bit of
|
|
// interframe.
|
|
//
|
// Revision 1.18 2003/02/09 02:24:33 mohor
|
// Revision 1.18 2003/02/09 02:24:33 mohor
|
// Bosch license warning added. Error counters finished. Overload frames
|
// Bosch license warning added. Error counters finished. Overload frames
|
// still need to be fixed.
|
// still need to be fixed.
|
//
|
//
|
// Revision 1.17 2003/02/04 17:24:41 mohor
|
// Revision 1.17 2003/02/04 17:24:41 mohor
|
| Line 298... |
Line 302... |
|
|
reg transmitting;
|
reg transmitting;
|
|
|
reg error_frame;
|
reg error_frame;
|
reg error_frame_q;
|
reg error_frame_q;
|
reg overload_frame;
|
|
reg enable_error_cnt2;
|
reg enable_error_cnt2;
|
reg [2:0] error_cnt1;
|
reg [2:0] error_cnt1;
|
reg [2:0] error_cnt2;
|
reg [2:0] error_cnt2;
|
reg [2:0] delayed_dominant_cnt;
|
reg [2:0] delayed_dominant_cnt;
|
reg enable_overload_cnt2;
|
reg enable_overload_cnt2;
|
|
reg overload_frame;
|
|
reg overload_frame_blocked;
|
reg [2:0] overload_cnt1;
|
reg [2:0] overload_cnt1;
|
reg [2:0] overload_cnt2;
|
reg [2:0] overload_cnt2;
|
reg tx;
|
reg tx;
|
reg crc_err;
|
reg crc_err;
|
|
|
| Line 435... |
Line 440... |
wire send_ack;
|
wire send_ack;
|
wire bit_err_exc1;
|
wire bit_err_exc1;
|
wire bit_err_exc2;
|
wire bit_err_exc2;
|
wire bit_err_exc3;
|
wire bit_err_exc3;
|
wire bit_err_exc4;
|
wire bit_err_exc4;
|
|
wire bit_err_exc5;
|
wire error_flag_over;
|
wire error_flag_over;
|
wire overload_flag_over;
|
wire overload_flag_over;
|
|
|
|
|
assign go_rx_idle = sample_point & sampled_bit & last_bit_of_inter;
|
assign go_rx_idle = sample_point & sampled_bit & last_bit_of_inter;
|
| Line 455... |
Line 461... |
rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
|
rx_data & (bit_cnt == ((limited_data_len<<3) - 1'b1)));
|
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt == 14);
|
assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt == 14);
|
assign go_rx_ack = sample_point & rx_crc_lim;
|
assign go_rx_ack = sample_point & rx_crc_lim;
|
assign go_rx_ack_lim = sample_point & rx_ack;
|
assign go_rx_ack_lim = sample_point & rx_ack;
|
assign go_rx_eof = sample_point & rx_ack_lim | (~reset_mode) & reset_mode_q;
|
assign go_rx_eof = sample_point & rx_ack_lim | (~reset_mode) & reset_mode_q;
|
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & (~go_overload_frame);
|
assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & (~overload_needed);
|
|
|
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
|
assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
|
assign error_frame_ended = (error_cnt2 == 7) & tx_point;
|
assign error_frame_ended = (error_cnt2 == 7) & tx_point;
|
assign overload_frame_ended = (overload_cnt2 == 7) & tx_point;
|
assign overload_frame_ended = (overload_cnt2 == 7) & tx_point;
|
|
|
assign go_overload_frame = ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & overload_needed |
|
assign go_overload_frame = ( ((sample_point & rx_eof & (eof_cnt == 6)) | error_frame_ended | overload_frame_ended) & overload_needed |
|
sample_point & (~sampled_bit) & rx_inter & (bit_cnt < 2) |
|
sample_point & (~sampled_bit) & rx_inter & (bit_cnt < 2) |
|
sample_point & (~sampled_bit) & ((error_cnt2 == 7) | (overload_cnt2 == 7))
|
sample_point & (~sampled_bit) & ((error_cnt2 == 7) | (overload_cnt2 == 7))
|
|
)
|
|
& (~overload_frame_blocked)
|
;
|
;
|
|
|
|
|
assign go_crc_enable = hard_sync | go_tx;
|
assign go_crc_enable = hard_sync | go_tx;
|
assign rst_crc_enable = go_rx_crc;
|
assign rst_crc_enable = go_rx_crc;
|
|
|
assign bit_de_stuff_set = go_rx_id1;
|
assign bit_de_stuff_set = go_rx_id1;
|
assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame;
|
assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame | go_overload_frame;
|
|
|
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
|
assign limited_data_len = (data_len < 8)? data_len : 4'h8;
|
|
|
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state;
|
assign ack_err = rx_ack & sample_point & sampled_bit & tx_state;
|
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx !== sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4);
|
assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx !== sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
|
assign bit_err_exc1 = tx_state & arbitration_field & tx;
|
assign bit_err_exc1 = tx_state & arbitration_field & tx;
|
assign bit_err_exc2 = rx_ack & tx;
|
assign bit_err_exc2 = rx_ack & tx;
|
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7);
|
assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7);
|
assign bit_err_exc4 = (error_frame & (error_cnt1 == 7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 7) & (~enable_overload_cnt2));
|
assign bit_err_exc4 = (error_frame & (error_cnt1 == 7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 7) & (~enable_overload_cnt2));
|
|
assign bit_err_exc5 = (error_frame & (error_cnt2 == 7)) | (overload_frame & (overload_cnt2 == 7));
|
|
|
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
|
assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
|
|
|
assign last_bit_of_inter = rx_inter & (bit_cnt == 2);
|
assign last_bit_of_inter = rx_inter & (bit_cnt == 2);
|
|
|
| Line 661... |
Line 670... |
// Rx eof state
|
// Rx eof state
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
rx_eof <= 1'b0;
|
rx_eof <= 1'b0;
|
else if (go_rx_inter | error_frame)
|
else if (go_rx_inter | error_frame | go_overload_frame)
|
rx_eof <=#Tp 1'b0;
|
rx_eof <=#Tp 1'b0;
|
else if (go_rx_eof)
|
else if (go_rx_eof)
|
rx_eof <=#Tp 1'b1;
|
rx_eof <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 801... |
Line 810... |
begin
|
begin
|
if (rst)
|
if (rst)
|
eof_cnt <= 0;
|
eof_cnt <= 0;
|
else if (sample_point)
|
else if (sample_point)
|
begin
|
begin
|
if (go_rx_inter | go_error_frame)
|
if (go_rx_inter | go_error_frame | go_overload_frame)
|
eof_cnt <=#Tp 0;
|
eof_cnt <=#Tp 0;
|
else if (rx_eof)
|
else if (rx_eof)
|
eof_cnt <=#Tp eof_cnt + 1'b1;
|
eof_cnt <=#Tp eof_cnt + 1'b1;
|
end
|
end
|
end
|
end
|
| Line 913... |
Line 922... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
ack_err_latched <= 1'b0;
|
ack_err_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
ack_err_latched <=#Tp 1'b0;
|
ack_err_latched <=#Tp 1'b0;
|
else if (ack_err)
|
else if (ack_err)
|
ack_err_latched <=#Tp 1'b1;
|
ack_err_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
bit_err_latched <= 1'b0;
|
bit_err_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
bit_err_latched <=#Tp 1'b0;
|
bit_err_latched <=#Tp 1'b0;
|
else if (bit_err)
|
else if (bit_err)
|
bit_err_latched <=#Tp 1'b1;
|
bit_err_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 988... |
Line 997... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
stuff_err_latched <= 1'b0;
|
stuff_err_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
stuff_err_latched <=#Tp 1'b0;
|
stuff_err_latched <=#Tp 1'b0;
|
else if (stuff_err)
|
else if (stuff_err)
|
stuff_err_latched <=#Tp 1'b1;
|
stuff_err_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1000... |
Line 1009... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
form_err_latched <= 1'b0;
|
form_err_latched <= 1'b0;
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
form_err_latched <=#Tp 1'b0;
|
form_err_latched <=#Tp 1'b0;
|
else if (form_err)
|
else if (form_err)
|
form_err_latched <=#Tp 1'b1;
|
form_err_latched <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1014... |
Line 1023... |
can_crc i_can_crc_rx
|
can_crc i_can_crc_rx
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.data(sampled_bit),
|
.data(sampled_bit),
|
.enable(crc_enable & sample_point & (~bit_de_stuff)),
|
.enable(crc_enable & sample_point & (~bit_de_stuff)),
|
.initialize(rx_eof),
|
.initialize(rx_eof | go_error_frame | go_overload_frame),
|
.crc(calculated_crc)
|
.crc(calculated_crc)
|
);
|
);
|
|
|
|
|
|
|
| Line 1060... |
Line 1069... |
.acceptance_mask_3(acceptance_mask_3),
|
.acceptance_mask_3(acceptance_mask_3),
|
/* End: This section is for EXTENDED mode */
|
/* End: This section is for EXTENDED mode */
|
|
|
.go_rx_crc_lim(go_rx_crc_lim),
|
.go_rx_crc_lim(go_rx_crc_lim),
|
.go_rx_inter(go_rx_inter),
|
.go_rx_inter(go_rx_inter),
|
|
.go_error_frame(go_error_frame),
|
|
|
.data0(tmp_fifo[0]),
|
.data0(tmp_fifo[0]),
|
.data1(tmp_fifo[1]),
|
.data1(tmp_fifo[1]),
|
.rtr1(rtr1),
|
.rtr1(rtr1),
|
.rtr2(rtr2),
|
.rtr2(rtr2),
|
| Line 1092... |
Line 1102... |
begin
|
begin
|
if (rst)
|
if (rst)
|
wr_fifo <= 1'b0;
|
wr_fifo <= 1'b0;
|
else if (reset_wr_fifo)
|
else if (reset_wr_fifo)
|
wr_fifo <=#Tp 1'b0;
|
wr_fifo <=#Tp 1'b0;
|
else if (go_rx_inter & id_ok & (~error_frame_ended)) // FIX ME !!! Look following line
|
// else if (go_rx_inter & id_ok & (~error_frame_ended)) // FIX ME !!! Look following line
|
// else if (go_rx_inter & id_ok & (~error_frame_ended) & (~tx_state)) FIX ME !!! This line is the correct one. The above line is for easier debugging only.
|
else if (go_rx_inter & id_ok & (~error_frame_ended) & (~tx_state)) // FIX ME !!! This line is the correct one. The above line is for easier debugging only.
|
wr_fifo <=#Tp 1'b1;
|
wr_fifo <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Header counter. Header length depends on the mode of operation and frame format.
|
// Header counter. Header length depends on the mode of operation and frame format.
|
| Line 1194... |
Line 1204... |
// Transmitting error frame.
|
// Transmitting error frame.
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_frame <= 1'b0;
|
error_frame <= 1'b0;
|
else if (reset_mode | error_frame_ended)
|
else if (reset_mode | error_frame_ended | go_overload_frame)
|
error_frame <=#Tp 1'b0;
|
error_frame <=#Tp 1'b0;
|
else if (go_error_frame)
|
else if (go_error_frame)
|
error_frame <=#Tp 1'b1;
|
error_frame <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1218... |
Line 1228... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_cnt1 <= 1'b0;
|
error_cnt1 <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
error_cnt1 <=#Tp 1'b0;
|
error_cnt1 <=#Tp 1'b0;
|
else if (error_frame & tx_point & (error_cnt1 < 7))
|
else if (error_frame & tx_point & (error_cnt1 < 7))
|
error_cnt1 <=#Tp error_cnt1 + 1'b1;
|
error_cnt1 <=#Tp error_cnt1 + 1'b1;
|
end
|
end
|
|
|
|
|
|
|
assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 7) | node_error_passive & sample_point & (passive_cnt == 5));
|
assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 7) | node_error_passive & sample_point & (passive_cnt == 5)) & (~enable_error_cnt2);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_flag_over_blocked <= 1'b0;
|
error_flag_over_blocked <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
error_flag_over_blocked <=#Tp 1'b0;
|
error_flag_over_blocked <=#Tp 1'b0;
|
else if (error_flag_over)
|
else if (error_flag_over)
|
error_flag_over_blocked <=#Tp 1'b1;
|
error_flag_over_blocked <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1245... |
Line 1255... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
enable_error_cnt2 <= 1'b0;
|
enable_error_cnt2 <= 1'b0;
|
else if (reset_mode | error_frame_ended | go_error_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
enable_error_cnt2 <=#Tp 1'b0;
|
enable_error_cnt2 <=#Tp 1'b0;
|
else if (error_frame & (error_flag_over & (~enable_error_cnt2) & sampled_bit))
|
else if (error_frame & (error_flag_over & sampled_bit))
|
enable_error_cnt2 <=#Tp 1'b1;
|
enable_error_cnt2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
error_cnt2 <= 0;
|
error_cnt2 <= 0;
|
else if (reset_mode | error_frame_ended | go_error_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
error_cnt2 <=#Tp 0;
|
error_cnt2 <=#Tp 0;
|
else if (enable_error_cnt2 & tx_point)
|
else if (enable_error_cnt2 & tx_point)
|
error_cnt2 <=#Tp error_cnt2 + 1'b1;
|
error_cnt2 <=#Tp error_cnt2 + 1'b1;
|
end
|
end
|
|
|
| Line 1279... |
Line 1289... |
// passive_cnt
|
// passive_cnt
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
passive_cnt <= 0;
|
passive_cnt <= 0;
|
else if (go_error_frame)
|
else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
|
passive_cnt <=#Tp 0;
|
passive_cnt <=#Tp 0;
|
else if (sample_point & (passive_cnt < 5))
|
else if (sample_point & (passive_cnt < 5))
|
begin
|
begin
|
if (error_frame_q & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
|
if (error_frame_q & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
|
passive_cnt <=#Tp passive_cnt + 1'b1;
|
passive_cnt <=#Tp passive_cnt + 1'b1;
|
| Line 1308... |
Line 1318... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_cnt1 <= 1'b0;
|
overload_cnt1 <= 1'b0;
|
else if (reset_mode | overload_frame_ended | go_error_frame)
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
overload_cnt1 <=#Tp 1'b0;
|
overload_cnt1 <=#Tp 1'b0;
|
else if (overload_frame & tx_point & (overload_cnt1 < 7))
|
else if (overload_frame & tx_point & (overload_cnt1 < 7))
|
overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
|
overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
|
end
|
end
|
|
|
|
|
assign overload_flag_over = sample_point & (overload_cnt1 == 7);
|
assign overload_flag_over = sample_point & (overload_cnt1 == 7) & (~enable_overload_cnt2);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
enable_overload_cnt2 <= 1'b0;
|
enable_overload_cnt2 <= 1'b0;
|
else if (reset_mode | overload_frame_ended | go_error_frame)
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
enable_overload_cnt2 <=#Tp 1'b0;
|
enable_overload_cnt2 <=#Tp 1'b0;
|
else if (overload_frame & (overload_flag_over & (~enable_overload_cnt2) & sampled_bit))
|
else if (overload_frame & (overload_flag_over & sampled_bit))
|
enable_overload_cnt2 <=#Tp 1'b1;
|
enable_overload_cnt2 <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
overload_cnt2 <= 0;
|
overload_cnt2 <= 0;
|
else if (reset_mode | overload_frame_ended | go_error_frame)
|
else if (reset_mode | overload_frame_ended | go_error_frame | go_overload_frame)
|
overload_cnt2 <=#Tp 0;
|
overload_cnt2 <=#Tp 0;
|
else if (enable_overload_cnt2 & tx_point)
|
else if (enable_overload_cnt2 & tx_point)
|
overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
|
overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
|
end
|
end
|
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
overload_frame_blocked <= 0;
|
|
else if (reset_mode | go_error_frame | go_rx_id1)
|
|
overload_frame_blocked <=#Tp 0;
|
|
else if (go_overload_frame & overload_frame) // This is a second sequential overload
|
|
overload_frame_blocked <=#Tp 1'b1;
|
|
end
|
|
|
|
|
assign send_ack = (~tx_state) & rx_ack & (~err);
|
assign send_ack = (~tx_state) & rx_ack & (~err);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx <= 1'b1;
|
tx <= 1'b1;
|
else if (reset_mode | error_frame_ended | overload_frame_ended) // Reset
|
else if (reset_mode) // Reset
|
tx <=#Tp 1'b1;
|
tx <=#Tp 1'b1;
|
else if (tx_point)
|
else if (tx_point)
|
begin
|
begin
|
if (tx_state) // Transmitting message
|
if (tx_state) // Transmitting message
|
tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
|
tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
|
else if (send_ack) // Acknowledge
|
else if (send_ack) // Acknowledge
|
tx <=#Tp 1'b0;
|
tx <=#Tp 1'b0;
|
|
else if (overload_frame) // Transmitting overload frame
|
|
begin
|
|
if (overload_cnt1 < 6)
|
|
tx <=#Tp 1'b0;
|
|
else
|
|
tx <=#Tp 1'b1;
|
|
end
|
else if (error_frame) // Transmitting error frame
|
else if (error_frame) // Transmitting error frame
|
begin
|
begin
|
if (error_cnt1 < 6)
|
if (error_cnt1 < 6)
|
begin
|
begin
|
if (node_error_passive)
|
if (node_error_passive)
|
| Line 1367... |
Line 1395... |
tx <=#Tp 1'b0;
|
tx <=#Tp 1'b0;
|
end
|
end
|
else
|
else
|
tx <=#Tp 1'b1;
|
tx <=#Tp 1'b1;
|
end
|
end
|
else if (overload_frame) // Transmitting overload frame
|
|
begin
|
|
if (overload_cnt1 < 6)
|
|
tx <=#Tp 1'b0;
|
|
else
|
|
tx <=#Tp 1'b1;
|
|
end
|
|
else
|
else
|
tx <=#Tp 1'b1;
|
tx <=#Tp 1'b1;
|
end
|
end
|
end
|
end
|
|
|
| Line 1461... |
Line 1482... |
((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
|
((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
|
((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
|
((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
|
( tx_point & rx_crc_lim ) | // crc
|
( tx_point & rx_crc_lim ) | // crc
|
(go_rx_idle ) | // at the end
|
(go_rx_idle ) | // at the end
|
(reset_mode ) |
|
(reset_mode ) |
|
(overload_frame ) | // FIX ME (not sure this is ok)
|
(overload_frame ) |
|
(error_frame ) ; // FIX ME (not sure this is ok)
|
(error_frame ) ;
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_pointer <= 'h0;
|
tx_pointer <= 'h0;
|
| Line 1475... |
Line 1496... |
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
|
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
|
tx_pointer <=#Tp tx_pointer + 1'b1;
|
tx_pointer <=#Tp tx_pointer + 1'b1;
|
end
|
end
|
|
|
|
|
assign tx_successful = transmitter & go_rx_inter & (~error_frame) & (~priority_lost);
|
assign tx_successful = transmitter & go_rx_inter & (~error_frame_ended) & (~overload_frame_ended) & (~priority_lost);
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
need_to_tx <= 1'b0;
|
need_to_tx <= 1'b0;
|
else if (tx_successful)
|
else if (tx_successful | node_bus_off)
|
need_to_tx <=#Tp 1'h0;
|
need_to_tx <=#Tp 1'h0;
|
else if (tx_request)
|
else if (tx_request)
|
need_to_tx <=#Tp 1'b1;
|
need_to_tx <=#Tp 1'b1;
|
end
|
end
|
|
|
| Line 1599... |
Line 1620... |
rx_err_cnt <= 'h0;
|
rx_err_cnt <= 'h0;
|
else if (reset_mode)
|
else if (reset_mode)
|
rx_err_cnt <=#Tp 'h0;
|
rx_err_cnt <=#Tp 'h0;
|
else
|
else
|
begin
|
begin
|
if ((rx_err_cnt < 1023) & (~transmitter))
|
if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
|
|
begin
|
|
if (rx_err_cnt > 127)
|
|
rx_err_cnt <=#Tp 127;
|
|
else
|
|
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
|
|
end
|
|
else if ((rx_err_cnt < 1023) & (~transmitter))
|
begin
|
begin
|
if (go_error_frame_q & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
|
if (go_error_frame_q & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
|
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
|
rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
|
else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2
|
else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2
|
(go_error_frame_q & rule5 ) | // 5
|
(go_error_frame_q & rule5 ) | // 5
|
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6
|
(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6
|
)
|
)
|
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
|
rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
|
end
|
end
|
else if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
|
|
begin
|
|
if (rx_err_cnt > 127)
|
|
rx_err_cnt <=#Tp 127;
|
|
else
|
|
rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
|
|
end
|
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
tx_err_cnt <= 'h0;
|
tx_err_cnt <= 'h0;
|
else if (reset_mode)
|
else if (reset_mode | node_bus_off)
|
tx_err_cnt <=#Tp 'h0;
|
tx_err_cnt <=#Tp 'h0;
|
else
|
else
|
begin
|
begin
|
if ((tx_err_cnt < 1023) & transmitter)
|
if ((tx_err_cnt > 0) & tx_successful)
|
|
tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
|
|
else if ((tx_err_cnt < 1023) & transmitter)
|
begin
|
begin
|
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) | // 6
|
if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) | // 6
|
(error_flag_over & (~error_flag_over_blocked) & rule5 ) | // 4 (rule 5 is the same as rule 4)
|
(error_flag_over & (~error_flag_over_blocked) & rule5 ) | // 4 (rule 5 is the same as rule 4)
|
(error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
|
(error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
|
)
|
)
|
tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
|
tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
|
end
|
end
|
else if ((tx_err_cnt > 0) & tx_successful)
|
|
tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
|
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
| Line 1681... |
Line 1702... |
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
recessive_cnt <= 1'b0;
|
recessive_cnt <= 1'b0;
|
else if (node_bus_off & sample_point & sampled_bit)
|
else if (sample_point)
|
|
begin
|
|
if (node_bus_off & sampled_bit)
|
recessive_cnt <=#Tp recessive_cnt + 1'b1;
|
recessive_cnt <=#Tp recessive_cnt + 1'b1;
|
else
|
else
|
recessive_cnt <=#Tp 0;
|
recessive_cnt <=#Tp 0;
|
end
|
end
|
|
end
|
|
|
|
|
assign recessive_cnt_ok = recessive_cnt == 128 * 11;
|
assign recessive_cnt_ok = recessive_cnt == 128 * 11;
|
|
|
|
|
