| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.23 2003/02/14 20:17:01 mohor
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// Several registers added. Not finished, yet.
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//
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// Revision 1.22 2003/02/12 14:23:59 mohor
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// Revision 1.22 2003/02/12 14:23:59 mohor
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// abort_tx added. Bit destuff fixed.
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// abort_tx added. Bit destuff fixed.
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//
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//
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// Revision 1.21 2003/02/11 00:56:06 mohor
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// Revision 1.21 2003/02/11 00:56:06 mohor
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// Wishbone interface added.
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// Wishbone interface added.
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| Line 150... |
Line 153... |
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/* Mode register */
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/* Mode register */
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reset_mode,
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reset_mode,
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listen_only_mode,
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acceptance_filter_mode,
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acceptance_filter_mode,
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self_test_mode,
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/* Command register */
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/* Command register */
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release_buffer,
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release_buffer,
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tx_request,
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tx_request,
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abort_tx,
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abort_tx,
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self_rx_request,
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single_shot_transmission,
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/* Error Warning Limit register */
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/* Error Warning Limit register */
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error_warning_limit,
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error_warning_limit,
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/* Rx Error Counter register */
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/* Rx Error Counter register */
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| Line 183... |
Line 190... |
receive_status,
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receive_status,
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tx_successful,
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tx_successful,
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need_to_tx,
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need_to_tx,
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overrun,
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overrun,
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info_empty,
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info_empty,
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go_error_frame,
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priority_lost,
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node_error_passive,
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node_error_active,
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/* This section is for BASIC and EXTENDED mode */
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/* This section is for BASIC and EXTENDED mode */
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/* Acceptance code register */
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/* Acceptance code register */
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acceptance_code_0,
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acceptance_code_0,
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| Line 242... |
Line 254... |
input [7:0] data_in;
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input [7:0] data_in;
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output [7:0] data_out;
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output [7:0] data_out;
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input reset_mode;
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input reset_mode;
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input listen_only_mode;
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input acceptance_filter_mode;
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input acceptance_filter_mode;
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input extended_mode;
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input extended_mode;
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input self_test_mode;
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/* Command register */
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/* Command register */
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input release_buffer;
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input release_buffer;
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input tx_request;
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input tx_request;
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input abort_tx;
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input abort_tx;
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input self_rx_request;
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input single_shot_transmission;
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/* Error Warning Limit register */
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/* Error Warning Limit register */
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input [7:0] error_warning_limit;
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input [7:0] error_warning_limit;
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/* Rx Error Counter register */
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/* Rx Error Counter register */
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| Line 274... |
Line 290... |
output receive_status;
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output receive_status;
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output tx_successful;
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output tx_successful;
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output need_to_tx;
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output need_to_tx;
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output overrun;
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output overrun;
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output info_empty;
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output info_empty;
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output go_error_frame;
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output priority_lost;
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output node_error_passive;
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output node_error_active;
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/* This section is for BASIC and EXTENDED mode */
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/* This section is for BASIC and EXTENDED mode */
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/* Acceptance code register */
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/* Acceptance code register */
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input [7:0] acceptance_code_0;
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input [7:0] acceptance_code_0;
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| Line 436... |
Line 456... |
wire go_rx_crc;
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wire go_rx_crc;
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wire go_rx_crc_lim;
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wire go_rx_crc_lim;
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wire go_rx_ack;
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wire go_rx_ack;
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wire go_rx_ack_lim;
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wire go_rx_ack_lim;
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wire go_rx_eof;
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wire go_rx_eof;
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wire go_error_frame;
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wire go_overload_frame;
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wire go_overload_frame;
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wire go_rx_inter;
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wire go_rx_inter;
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wire go_crc_enable;
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wire go_crc_enable;
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wire rst_crc_enable;
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wire rst_crc_enable;
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| Line 462... |
Line 481... |
wire bit_err;
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wire bit_err;
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wire ack_err;
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wire ack_err;
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wire stuff_err;
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wire stuff_err;
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// of intermission, it starts reading the identifier (and transmitting its own).
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// of intermission, it starts reading the identifier (and transmitting its own).
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wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
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wire overload_needed = 0; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
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// be send in a row. This is not implemented because host can not send an overload request. FIX ME !!!!
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// be send in a row. This is not implemented because host can not send an overload request.
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wire id_ok; // If received ID matches ID set in registers
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wire id_ok; // If received ID matches ID set in registers
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wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
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wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
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wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
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wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
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| Line 547... |
Line 566... |
assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame | go_overload_frame;
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assign bit_de_stuff_reset = go_rx_crc_lim | reset_mode | go_error_frame | go_overload_frame;
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assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
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assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
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assign limited_data_len = (data_len < 8)? data_len : 4'h8;
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assign limited_data_len = (data_len < 8)? data_len : 4'h8;
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assign ack_err = rx_ack & sample_point & sampled_bit & tx_state;
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assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
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assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx !== sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
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assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx !== sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5);
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assign bit_err_exc1 = tx_state & arbitration_field & tx;
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assign bit_err_exc1 = tx_state & arbitration_field & tx;
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assign bit_err_exc2 = rx_ack & tx;
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assign bit_err_exc2 = rx_ack & tx;
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assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7);
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assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 7);
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assign bit_err_exc4 = (error_frame & (error_cnt1 == 7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 7) & (~enable_overload_cnt2));
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assign bit_err_exc4 = (error_frame & (error_cnt1 == 7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 7) & (~enable_overload_cnt2));
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| Line 828... |
Line 847... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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byte_cnt <= 0;
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byte_cnt <= 0;
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else if (reset_mode | write_data_to_tmp_fifo)
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else if (write_data_to_tmp_fifo)
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byte_cnt <=#Tp byte_cnt + 1;
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byte_cnt <=#Tp byte_cnt + 1;
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else if (sample_point & go_rx_crc_lim)
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else if (reset_mode | (sample_point & go_rx_crc_lim))
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byte_cnt <=#Tp 0;
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byte_cnt <=#Tp 0;
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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| Line 1178... |
Line 1197... |
begin
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begin
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if (rst)
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if (rst)
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wr_fifo <= 1'b0;
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wr_fifo <= 1'b0;
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else if (reset_wr_fifo)
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else if (reset_wr_fifo)
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wr_fifo <=#Tp 1'b0;
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wr_fifo <=#Tp 1'b0;
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else if (go_rx_inter & id_ok & (~error_frame_ended)) // FIX ME !!! Look following line
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else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) | self_rx_request))
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// else if (go_rx_inter & id_ok & (~error_frame_ended) & (~tx_state)) // FIX ME !!! This line is the correct one. The above line is for easier debugging only.
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wr_fifo <=#Tp 1'b1;
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wr_fifo <=#Tp 1'b1;
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end
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end
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// Header counter. Header length depends on the mode of operation and frame format.
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// Header counter. Header length depends on the mode of operation and frame format.
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| Line 1439... |
Line 1457... |
else if (go_overload_frame & overload_frame) // This is a second sequential overload
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else if (go_overload_frame & overload_frame) // This is a second sequential overload
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overload_frame_blocked <=#Tp 1'b1;
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overload_frame_blocked <=#Tp 1'b1;
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end
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end
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assign send_ack = (~tx_state) & rx_ack & (~err);
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assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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| Line 1552... |
Line 1570... |
else
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else
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tx_bit = basic_chain[tx_pointer];
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tx_bit = basic_chain[tx_pointer];
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end
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end
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end
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end
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assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & r_tx_data_0[0] & tx_pointer == 38 ) | // arbitration + control for extended format
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assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & tx_pointer == 38 ) | // arbitration + control for extended format
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((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & (~r_tx_data_0[0]) & tx_pointer == 18 ) | // arbitration + control for extended format
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((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 18 ) | // arbitration + control for standard format
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((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 18 ) | // arbitration + control for standard format
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((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
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((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == (8 * tx_data_0[3:0] - 1)) | // data
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((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
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((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == (8 * tx_data_1[3:0] - 1)) | // data
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( tx_point & rx_crc_lim ) | // crc
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( tx_point & rx_crc_lim ) | // crc
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(go_rx_idle ) | // at the end
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(go_rx_idle ) | // at the end
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| Line 1574... |
Line 1592... |
else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
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else if (go_early_tx | (tx_point & tx_state & (~bit_de_stuff_tx)))
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tx_pointer <=#Tp tx_pointer + 1'b1;
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tx_pointer <=#Tp tx_pointer + 1'b1;
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end
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end
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assign tx_successful = transmitter & go_rx_inter & (~error_frame_ended) & (~overload_frame_ended) & (~priority_lost);
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assign tx_successful = transmitter & go_rx_inter & ((~error_frame_ended) & (~overload_frame_ended) & (~priority_lost) | single_shot_transmission);
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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| Line 1589... |
Line 1607... |
need_to_tx <=#Tp 1'b1;
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need_to_tx <=#Tp 1'b1;
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end
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end
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assign go_early_tx = need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
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assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
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assign go_tx = need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
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assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
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// Tx state
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// Tx state
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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| Line 1700... |
Line 1718... |
rx_err_cnt <=#Tp {1'b0, data_in};
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rx_err_cnt <=#Tp {1'b0, data_in};
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else if (set_reset_mode)
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else if (set_reset_mode)
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rx_err_cnt <=#Tp 'h0;
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rx_err_cnt <=#Tp 'h0;
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else
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else
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begin
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begin
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if (~listen_only_mode)
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begin
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if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
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if ((~transmitter) & go_rx_ack_lim & (~err) & (rx_err_cnt > 0))
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begin
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begin
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if (rx_err_cnt > 127)
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if (rx_err_cnt > 127)
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rx_err_cnt <=#Tp 127;
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rx_err_cnt <=#Tp 127;
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else
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else
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| Line 1719... |
Line 1739... |
)
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)
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rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
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rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
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end
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end
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end
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end
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end
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end
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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| Line 1769... |
Line 1790... |
else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 128)) & (error_frame_ended | (~reset_mode) & reset_mode_q) & (~node_bus_off))
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else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 128)) & (error_frame_ended | (~reset_mode) & reset_mode_q) & (~node_bus_off))
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node_error_passive <=#Tp 1'b1;
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node_error_passive <=#Tp 1'b1;
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end
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end
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assign node_error_active = ~(node_error_passive | node_bus_off);
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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node_bus_off <= 1'b0;
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node_bus_off <= 1'b0;
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else if ((rx_err_cnt == 0) & (tx_err_cnt == 0) & (~reset_mode) | (we_tx_err_cnt & (data_in < 255)))
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else if ((rx_err_cnt == 0) & (tx_err_cnt == 0) & (~reset_mode) | (we_tx_err_cnt & (data_in < 255)))
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