| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.25 2003/02/19 14:44:03 mohor
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// CAN core finished. Host interface added. Registers finished.
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// Synchronization to the wishbone finished.
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//
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// Revision 1.24 2003/02/18 00:10:15 mohor
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// Revision 1.24 2003/02/18 00:10:15 mohor
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// Most of the registers added. Registers "arbitration lost capture", "error code
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// Most of the registers added. Registers "arbitration lost capture", "error code
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// capture" + few more still need to be added.
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// capture" + few more still need to be added.
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//
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//
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// Revision 1.23 2003/02/14 20:17:01 mohor
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// Revision 1.23 2003/02/14 20:17:01 mohor
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| Line 452... |
Line 456... |
reg node_bus_off_q;
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reg node_bus_off_q;
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reg ack_err_latched;
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reg ack_err_latched;
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reg bit_err_latched;
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reg bit_err_latched;
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reg stuff_err_latched;
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reg stuff_err_latched;
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reg form_err_latched;
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reg form_err_latched;
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reg rule5;
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reg rule3_exc1_1;
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reg rule3_exc1_1;
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reg rule3_exc1_2;
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reg rule3_exc1_2;
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reg rule3_exc2;
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reg rule3_exc2;
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reg suspend;
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reg suspend;
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reg susp_cnt_en;
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reg susp_cnt_en;
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reg [2:0] susp_cnt;
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reg [2:0] susp_cnt;
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reg go_error_frame_q;
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reg error_flag_over_blocked;
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reg error_flag_over_blocked;
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reg [7:0] error_capture_code;
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reg [7:0] error_capture_code;
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reg [7:6] error_capture_code_type;
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reg [7:6] error_capture_code_type;
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reg error_capture_code_blocked;
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reg error_capture_code_blocked;
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| Line 472... |
Line 474... |
wire error_capture_code_direction;
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wire error_capture_code_direction;
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wire bit_de_stuff;
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wire bit_de_stuff;
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wire bit_de_stuff_tx;
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wire bit_de_stuff_tx;
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wire rule5;
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/* Rx state machine */
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/* Rx state machine */
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wire go_rx_idle;
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wire go_rx_idle;
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wire go_rx_id1;
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wire go_rx_id1;
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wire go_rx_rtr1;
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wire go_rx_rtr1;
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| Line 1069... |
Line 1072... |
else if (bit_err)
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else if (bit_err)
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bit_err_latched <=#Tp 1'b1;
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bit_err_latched <=#Tp 1'b1;
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end
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end
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// Rule 5 (Fault confinement).
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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rule5 <= 1'b0;
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else if (reset_mode | error_flag_over)
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rule5 <=#Tp 1'b0;
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else if ((~node_error_passive) & bit_err & (~bit_err_latched) & (error_frame & (error_cnt1 < 7) |
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overload_frame & (overload_cnt1 < 7) )
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)
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rule5 <=#Tp 1'b1;
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end
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// Rule 5 (Fault confinement).
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assign rule5 = (~node_error_passive) & bit_err & (error_frame & (error_cnt1 < 7) |
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overload_frame & (overload_cnt1 < 7) );
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// Rule 3 exception 1 - first part (Fault confinement).
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// Rule 3 exception 1 - first part (Fault confinement).
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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| Line 1347... |
Line 1341... |
if (sample_point)
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if (sample_point)
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error_frame_q <=#Tp error_frame;
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error_frame_q <=#Tp error_frame;
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end
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end
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always @ (posedge clk)
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begin
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go_error_frame_q <=#Tp go_error_frame;
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end
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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error_cnt1 <= 1'b0;
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error_cnt1 <= 1'b0;
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else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
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else if (reset_mode | error_frame_ended | go_error_frame | go_overload_frame)
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| Line 1805... |
Line 1793... |
else
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else
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rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
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rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
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end
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end
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else if ((rx_err_cnt < 248) & (~transmitter)) // 248 + 8 = 256
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else if ((rx_err_cnt < 248) & (~transmitter)) // 248 + 8 = 256
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begin
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begin
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if (go_error_frame_q & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
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if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
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rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
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rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
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else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2
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else if ( (error_frame & sample_point & (~sampled_bit) & (error_cnt1 == 7) & (~rx_err_cnt_blocked) ) | // 2
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(go_error_frame_q & rule5 ) | // 5
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(go_error_frame & rule5 ) | // 5
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(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6
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(error_frame & sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) // 6
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)
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)
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rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
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rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
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end
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end
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end
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end
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| Line 1833... |
Line 1821... |
else if ((tx_err_cnt > 0) & (tx_successful | bus_free))
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else if ((tx_err_cnt > 0) & (tx_successful | bus_free))
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tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
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tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
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else if (transmitter)
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else if (transmitter)
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begin
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begin
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if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) | // 6
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if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 7) ) | // 6
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(error_flag_over & (~error_flag_over_blocked) & rule5 ) | // 4 (rule 5 is the same as rule 4)
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(go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
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(error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
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(error_flag_over & (~error_flag_over_blocked) & (~rule3_exc1_2) & (~rule3_exc2) ) // 3
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)
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)
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tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
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tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
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end
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end
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end
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end
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| Line 1861... |
Line 1849... |
begin
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begin
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if (rst)
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if (rst)
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node_error_passive <= 1'b0;
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node_error_passive <= 1'b0;
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else if ((rx_err_cnt < 128) & (tx_err_cnt < 128) & error_frame_ended)
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else if ((rx_err_cnt < 128) & (tx_err_cnt < 128) & error_frame_ended)
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node_error_passive <=#Tp 1'b0;
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node_error_passive <=#Tp 1'b0;
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else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 128)) & (error_frame_ended | (~reset_mode) & reset_mode_q) & (~node_bus_off))
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else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
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node_error_passive <=#Tp 1'b1;
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node_error_passive <=#Tp 1'b1;
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end
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end
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assign node_error_active = ~(node_error_passive | node_bus_off);
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assign node_error_active = ~(node_error_passive | node_bus_off);
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