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https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [tags/] [rel_6/] [rtl/] [verilog/] [can_bsp.v] - Diff between revs 44 and 45
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| Rev 44 |
Rev 45 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.26 2003/02/19 23:21:54 mohor
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// When bit error occured while active error flag was transmitted, counter was
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// not incremented.
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//
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// Revision 1.25 2003/02/19 14:44:03 mohor
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// Revision 1.25 2003/02/19 14:44:03 mohor
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// CAN core finished. Host interface added. Registers finished.
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// CAN core finished. Host interface added. Registers finished.
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// Synchronization to the wishbone finished.
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// Synchronization to the wishbone finished.
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//
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//
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// Revision 1.24 2003/02/18 00:10:15 mohor
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// Revision 1.24 2003/02/18 00:10:15 mohor
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| Line 389... |
Line 393... |
reg rx_crc_lim;
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reg rx_crc_lim;
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reg rx_ack;
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reg rx_ack;
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reg rx_ack_lim;
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reg rx_ack_lim;
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reg rx_eof;
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reg rx_eof;
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reg rx_inter;
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reg rx_inter;
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reg go_early_tx_latched;
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reg rtr1;
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reg rtr1;
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reg ide;
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reg ide;
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reg rtr2;
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reg rtr2;
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reg [14:0] crc_in;
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reg [14:0] crc_in;
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Line 1523... |
tx <=#Tp 1'b1;
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tx <=#Tp 1'b1;
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end
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end
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (tx_point)
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if (tx_point)
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tx_q <=#Tp tx;
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tx_q <=#Tp tx & (~go_early_tx_latched);
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end
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end
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/* Delayed tx point */
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/* Delayed tx point */
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always @ (posedge clk)
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always @ (posedge clk)
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Line 1638... |
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assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
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assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
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assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
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assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend) & (go_early_tx | rx_idle);
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// go_early_tx latched (for proper bit_de_stuff generation)
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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go_early_tx_latched <= 1'b0;
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else if (tx_point_q)
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go_early_tx_latched <=#Tp 1'b0;
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else if (go_early_tx)
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go_early_tx_latched <=#Tp 1'b1;
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end
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// Tx state
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// Tx state
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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tx_state <= 1'b0;
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tx_state <= 1'b0;
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