| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.29 2003/06/11 14:21:35 mohor
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// When switching to tx, sync stage is overjumped.
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//
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// Revision 1.28 2003/03/01 22:53:33 mohor
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// Revision 1.28 2003/03/01 22:53:33 mohor
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// Actel APA ram supported.
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// Actel APA ram supported.
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//
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//
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// Revision 1.27 2003/02/20 00:26:02 mohor
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// Revision 1.27 2003/02/20 00:26:02 mohor
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// When a dominant bit was detected at the third bit of the intermission and
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// When a dominant bit was detected at the third bit of the intermission and
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| Line 556... |
Line 559... |
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wire [18:0] basic_chain;
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wire [18:0] basic_chain;
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wire [63:0] basic_chain_data;
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wire [63:0] basic_chain_data;
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wire [18:0] extended_chain_std;
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wire [18:0] extended_chain_std;
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wire [38:0] extended_chain_ext;
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wire [38:0] extended_chain_ext;
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wire [63:0] extended_chain_data;
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wire [63:0] extended_chain_data_std;
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wire [63:0] extended_chain_data_ext;
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wire rst_tx_pointer;
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wire rst_tx_pointer;
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wire [7:0] r_tx_data_0;
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wire [7:0] r_tx_data_0;
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wire [7:0] r_tx_data_1;
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wire [7:0] r_tx_data_1;
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| Line 1578... |
Line 1582... |
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assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
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assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
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assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
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assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
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assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
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assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
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assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
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assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
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assign extended_chain_data = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
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assign extended_chain_data_std = {r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3};
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assign extended_chain_data_ext = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
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always @ (extended_mode or rx_data or tx_pointer or extended_chain_data or rx_crc or r_calculated_crc or
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always @ (extended_mode or rx_data or tx_pointer or extended_chain_data_std or extended_chain_data_ext or rx_crc or r_calculated_crc or
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r_tx_data_0 or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
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r_tx_data_0 or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
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finish_msg)
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finish_msg)
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begin
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begin
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if (extended_mode)
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if (extended_mode)
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begin
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begin
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if (rx_data) // data stage
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if (rx_data) // data stage
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tx_bit = extended_chain_data[tx_pointer];
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if (r_tx_data_0[0]) // Extended frame
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tx_bit = extended_chain_data_ext[tx_pointer];
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else
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tx_bit = extended_chain_data_std[tx_pointer];
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else if (rx_crc)
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else if (rx_crc)
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tx_bit = r_calculated_crc[tx_pointer];
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tx_bit = r_calculated_crc[tx_pointer];
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else if (finish_msg)
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else if (finish_msg)
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tx_bit = 1'b1;
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tx_bit = 1'b1;
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else
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else
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