Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2002/12/25 23:44:16 mohor
|
|
// Commented lines removed.
|
|
//
|
// Revision 1.2 2002/12/25 14:17:00 mohor
|
// Revision 1.2 2002/12/25 14:17:00 mohor
|
// Synchronization working.
|
// Synchronization working.
|
//
|
//
|
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
|
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
|
// Initial
|
// Initial
|
Line 107... |
Line 110... |
input [3:0] time_segment1;
|
input [3:0] time_segment1;
|
input [2:0] time_segment2;
|
input [2:0] time_segment2;
|
input triple_sampling;
|
input triple_sampling;
|
|
|
/* Output signals from this module */
|
/* Output signals from this module */
|
output take_sample;
|
output take_sample; // NOT USED, YET
|
output clk_en;
|
output clk_en;
|
|
|
input idle;
|
input idle;
|
|
|
/* bit stream processor (can_bsp.v) */
|
/* bit stream processor (can_bsp.v) */
|
Line 127... |
Line 130... |
reg sync;
|
reg sync;
|
reg seg1;
|
reg seg1;
|
reg seg2;
|
reg seg2;
|
reg resync_latched;
|
reg resync_latched;
|
reg sample_pulse;
|
reg sample_pulse;
|
|
reg [1:0] sample;
|
|
|
wire go_sync;
|
wire go_sync;
|
wire go_seg1;
|
wire go_seg1;
|
wire go_seg2;
|
wire go_seg2;
|
wire [8:0] preset_cnt;
|
wire [8:0] preset_cnt;
|
Line 166... |
Line 170... |
end
|
end
|
|
|
|
|
|
|
/* Changing states */
|
/* Changing states */
|
assign go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));
|
//assign go_sync = clk_en & (seg2 & (~resync) & ((quant_cnt == time_segment2)));
|
|
assign go_sync = clk_en & (seg2 & ((quant_cnt == time_segment2)));
|
assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
|
assign go_seg1 = clk_en & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
|
assign go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + delay)));
|
assign go_seg2 = clk_en & (seg1 & (quant_cnt == (time_segment1 + delay)));
|
|
|
|
|
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
|
/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
|
Line 249... |
Line 254... |
|
|
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
|
// If early edge appears within this window (in seg2 stage), phase error is fully compensated
|
assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
|
assign sync_window = ((time_segment2 - quant_cnt) < ( sync_jump_width + 1));
|
|
|
|
|
// Sampling data
|
// Sampling data (memorizing two samples all the time).
|
|
always @ (posedge clk or posedge rst)
|
|
begin
|
|
if (rst)
|
|
sample <= 2'b11;
|
|
else if (clk_en)
|
|
sample <= {sample[0], rx};
|
|
end
|
|
|
|
|
|
// When enabled, tripple sampling is done here.
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
begin
|
begin
|
sampled_bit <= 1;
|
sampled_bit <= 1;
|
sample_pulse <= 0;
|
sample_pulse <= 0;
|
end
|
end
|
else if (go_seg2)
|
else if (clk_en)
|
|
begin
|
|
if (seg1 & (quant_cnt == (time_segment1 + delay)))
|
begin
|
begin
|
sampled_bit <=#Tp rx;
|
|
sample_pulse <=#Tp 1;
|
sample_pulse <=#Tp 1;
|
|
if (triple_sampling)
|
|
sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
|
|
else
|
|
sampled_bit <=#Tp rx;
|
|
end
|
end
|
end
|
else
|
else
|
sample_pulse <=#Tp 0; // Sample pulse is for development purposes only. REMOVE ME.
|
sample_pulse <=#Tp 0; // Sample pulse is for development purposes only. REMOVE ME.
|
end
|
end
|
|
|