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//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.33  2003/06/11 14:21:35  mohor

// Revision 1.33  2003/06/11 14:21:35  mohor

// When switching to tx, sync stage is overjumped.

// When switching to tx, sync stage is overjumped.

//

//

// Revision 1.32  2003/06/09 11:32:36  mohor

// Revision 1.32  2003/06/09 11:32:36  mohor

// Ports added for the CAN_BIST.

// Ports added for the CAN_BIST.

/* End: Tx data registers */

/* End: Tx data registers */

wire         cs;

wire         cs;

/* Output signals from can_btl module */

/* Output signals from can_btl module */

wire         sample_point;

wire         sample_point;

wire         sampled_bit;

wire         sampled_bit;

wire         sampled_bit_q;

wire         sampled_bit_q;

wire         tx_point;

wire         tx_point;

wire         hard_sync;

wire         hard_sync;

wire         rst;

wire         rst;

wire         we;

wire         we;

wire   [7:0] addr;

wire   [7:0] addr;

wire   [7:0] data_in;

wire   [7:0] data_in;

reg    [7:0] data_out;

reg    [7:0] data_out;

/* Connecting can_registers module */

/* Connecting can_registers module */

can_registers i_can_registers

can_registers i_can_registers

(

(

  .clk(clk_i),

  .clk(clk_i),

/* Connecting can_btl module */

/* Connecting can_btl module */

can_btl i_can_btl

can_btl i_can_btl

(

(

  .clk(clk_i),

  .clk(clk_i),

  .rst(rst),

  .rst(rst),

  /* Mode register */

  /* Mode register */

  .reset_mode(reset_mode),

  .reset_mode(reset_mode),

  /* Bus Timing 0 register */

  /* Bus Timing 0 register */

  .time_segment1(time_segment1),

  .time_segment1(time_segment1),

  .time_segment2(time_segment2),

  .time_segment2(time_segment2),

  .triple_sampling(triple_sampling),

  .triple_sampling(triple_sampling),

  /* Output signals from this module */

  /* Output signals from this module */

  .sample_point(sample_point),

  .sample_point(sample_point),

  .sampled_bit(sampled_bit),

  .sampled_bit(sampled_bit),

  .sampled_bit_q(sampled_bit_q),

  .sampled_bit_q(sampled_bit_q),

  .tx_point(tx_point),

  .tx_point(tx_point),

  .hard_sync(hard_sync),

  .hard_sync(hard_sync),

    end

    end

end

end

`ifdef CAN_WISHBONE_IF

`ifdef CAN_WISHBONE_IF

  // Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain. 

  // Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain. 

  always @ (posedge clk_i or posedge rst)

  always @ (posedge clk_i or posedge rst)

  begin

  begin

    if (rst)

    if (rst)

  assign data_in   = port_0_io;

  assign data_in   = port_0_io;

  assign port_0_io = (cs_can_i & rd_i)? data_out : 8'hz;

  assign port_0_io = (cs_can_i & rd_i)? data_out : 8'hz;

`endif

`endif

endmodule

endmodule

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