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https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [tags/] [rel_7/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 50 and 52
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Rev 52 |
Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.28 2003/03/05 15:00:49 mohor
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// Top level signal names changed.
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//
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// Revision 1.27 2003/03/01 22:48:26 mohor
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// Revision 1.27 2003/03/01 22:48:26 mohor
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// Actel APA ram supported.
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// Actel APA ram supported.
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//
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//
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// Revision 1.26 2003/02/19 14:43:17 mohor
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// Revision 1.26 2003/02/19 14:43:17 mohor
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// CAN core finished. Host interface added. Registers finished.
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// CAN core finished. Host interface added. Registers finished.
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Line 168... |
Line 171... |
reg wb_we_i;
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reg wb_we_i;
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reg [7:0] wb_adr_i;
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reg [7:0] wb_adr_i;
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reg clk;
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reg clk;
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reg rx;
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reg rx;
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wire tx;
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wire tx;
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wire tx_oen;
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wire wb_ack_o;
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wire wb_ack_o;
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wire irq;
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wire irq;
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wire clkout;
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wire clkout;
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wire tx_3st;
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wire rx_and_tx;
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wire rx_and_tx;
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integer start_tb;
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integer start_tb;
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reg [7:0] tmp_data;
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reg [7:0] tmp_data;
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reg delayed_tx;
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reg delayed_tx;
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Line 200... |
Line 201... |
.wb_adr_i(wb_adr_i),
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.wb_adr_i(wb_adr_i),
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.wb_ack_o(wb_ack_o),
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.wb_ack_o(wb_ack_o),
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.clk_i(clk),
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.clk_i(clk),
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.rx_i(rx_and_tx),
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.rx_i(rx_and_tx),
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.tx_o(tx),
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.tx_o(tx),
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.tx_oen(tx_oen),
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.irq_o(irq),
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.irq_o(irq),
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.clkout_o(clkout)
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.clkout_o(clkout)
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);
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);
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assign tx_3st = tx_oen? 1'bz : tx;
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// Generate wishbone clock signal 10 MHz
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// Generate wishbone clock signal 10 MHz
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initial
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initial
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begin
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begin
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Line 248... |
Line 247... |
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// Generating delayed tx signal (CAN transciever delay)
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// Generating delayed tx signal (CAN transciever delay)
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always
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always
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begin
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begin
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wait (tx_3st);
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wait (tx);
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repeat (4*BRP) @ (posedge clk); // 4 time quants delay
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repeat (4*BRP) @ (posedge clk); // 4 time quants delay
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#1 delayed_tx = tx_3st;
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#1 delayed_tx = tx;
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wait (~tx_3st);
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wait (~tx);
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repeat (4*BRP) @ (posedge clk); // 4 time quants delay
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repeat (4*BRP) @ (posedge clk); // 4 time quants delay
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#1 delayed_tx = tx_3st;
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#1 delayed_tx = tx;
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end
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end
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//assign rx_and_tx = rx & delayed_tx; FIX ME !!!
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//assign rx_and_tx = rx & delayed_tx; FIX ME !!!
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assign rx_and_tx = rx & (delayed_tx | tx_bypassed); // When this signal is on, tx is not looped back to the rx.
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assign rx_and_tx = rx & (delayed_tx | tx_bypassed); // When this signal is on, tx is not looped back to the rx.
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