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https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [tags/] [rel_7/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 63 and 68
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Rev 63 |
Rev 68 |
Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.33 2003/03/14 19:37:30 mohor
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// ALE changes on negedge of clk.
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//
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// Revision 1.32 2003/03/12 05:57:36 mohor
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// Revision 1.32 2003/03/12 05:57:36 mohor
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// Bidirectional port_0_i changed to port_0_io.
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// Bidirectional port_0_i changed to port_0_io.
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// input cs_can changed to cs_can_i.
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// input cs_can changed to cs_can_i.
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//
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//
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// Revision 1.31 2003/03/12 04:40:00 mohor
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// Revision 1.31 2003/03/12 04:40:00 mohor
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Line 238... |
Line 241... |
`endif
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`endif
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.cs_can_i(cs_can),
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.cs_can_i(cs_can),
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.clk_i(clk),
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.clk_i(clk),
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.rx_i(rx_and_tx),
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.rx_i(rx_and_tx),
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.tx_o(tx),
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.tx_o(tx),
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.irq_o(irq),
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.irq_on(irq),
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.clkout_o(clkout)
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.clkout_o(clkout)
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);
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);
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`ifdef CAN_WISHBONE_IF
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`ifdef CAN_WISHBONE_IF
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