| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.31 2003/06/16 14:31:29 tadejm
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// Bit stuffing corrected when stuffing comes at the end of the crc.
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//
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// Revision 1.30 2003/06/16 13:57:58 mohor
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// Revision 1.30 2003/06/16 13:57:58 mohor
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// tx_point generated one clk earlier. rx_i registered. Data corrected when
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// tx_point generated one clk earlier. rx_i registered. Data corrected when
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// using extended mode.
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// using extended mode.
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//
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//
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// Revision 1.29 2003/06/11 14:21:35 mohor
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// Revision 1.29 2003/06/11 14:21:35 mohor
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| Line 170... |
Line 173... |
sample_point,
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sample_point,
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sampled_bit,
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sampled_bit,
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sampled_bit_q,
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sampled_bit_q,
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tx_point,
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tx_point,
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hard_sync,
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hard_sync,
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go_seg1,
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addr,
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addr,
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data_in,
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data_in,
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data_out,
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data_out,
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fifo_selected,
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fifo_selected,
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| Line 213... |
Line 215... |
/* Clock Divider register */
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/* Clock Divider register */
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extended_mode,
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extended_mode,
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rx_idle,
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rx_idle,
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transmitting,
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transmitting,
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overjump_sync_seg,
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last_bit_of_inter,
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last_bit_of_inter,
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set_reset_mode,
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set_reset_mode,
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node_bus_off,
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node_bus_off,
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error_status,
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error_status,
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rx_err_cnt,
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rx_err_cnt,
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| Line 286... |
Line 287... |
input sample_point;
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input sample_point;
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input sampled_bit;
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input sampled_bit;
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input sampled_bit_q;
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input sampled_bit_q;
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input tx_point;
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input tx_point;
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input hard_sync;
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input hard_sync;
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input go_seg1;
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input [7:0] addr;
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input [7:0] addr;
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input [7:0] data_in;
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input [7:0] data_in;
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output [7:0] data_out;
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output [7:0] data_out;
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input fifo_selected;
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input fifo_selected;
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| Line 325... |
Line 325... |
/* Tx Error Counter register */
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/* Tx Error Counter register */
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input we_tx_err_cnt;
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input we_tx_err_cnt;
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output rx_idle;
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output rx_idle;
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output transmitting;
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output transmitting;
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output overjump_sync_seg;
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output last_bit_of_inter;
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output last_bit_of_inter;
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output set_reset_mode;
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output set_reset_mode;
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output node_bus_off;
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output node_bus_off;
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output error_status;
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output error_status;
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output [8:0] rx_err_cnt;
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output [8:0] rx_err_cnt;
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| Line 432... |
Line 431... |
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reg [2:0] eof_cnt;
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reg [2:0] eof_cnt;
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reg [2:0] passive_cnt;
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reg [2:0] passive_cnt;
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reg transmitting;
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reg transmitting;
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reg transmitting_q;
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reg overjump_sync_seg;
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reg error_frame;
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reg error_frame;
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reg error_frame_q;
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reg error_frame_q;
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reg enable_error_cnt2;
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reg enable_error_cnt2;
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reg [2:0] error_cnt1;
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reg [2:0] error_cnt1;
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| Line 1071... |
Line 1068... |
end
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end
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// Conditions for form error
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// Conditions for form error
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assign form_err = sample_point & ( ((~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) ) |
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assign form_err = sample_point & ( ((~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1) ) |
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( rx_crc_lim & (~sampled_bit) ) |
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((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
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( rx_ack_lim & (~sampled_bit) ) |
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( rx_ack_lim & (~sampled_bit) ) |
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((eof_cnt < 6) & rx_eof & (~sampled_bit) & (~tx_state) ) |
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((eof_cnt < 6) & rx_eof & (~sampled_bit) & (~tx_state) ) |
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( & rx_eof & (~sampled_bit) & tx_state )
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( & rx_eof & (~sampled_bit) & tx_state )
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);
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);
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| Line 1721... |
Line 1718... |
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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transmitting_q <= 1'b0;
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else if (go_seg1)
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transmitting_q <=#Tp transmitting;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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overjump_sync_seg <= 1'b0;
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else if (transmitting & (~transmitting_q))
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overjump_sync_seg <=#Tp 1'b1;
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else
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overjump_sync_seg <=#Tp 1'b0;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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suspend <= 0;
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suspend <= 0;
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else if (reset_mode | (sample_point & (susp_cnt == 7)))
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else if (reset_mode | (sample_point & (susp_cnt == 7)))
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suspend <=#Tp 0;
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suspend <=#Tp 0;
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else if (go_rx_inter & transmitter & node_error_passive)
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else if (go_rx_inter & transmitter & node_error_passive)
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suspend <=#Tp 1'b1;
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suspend <=#Tp 1'b1;
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