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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 9 and 10

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Rev 9 Rev 10
Line 43... Line 43... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.6  2002/12/27 00:12:48  mohor
 
 
 
// Header changed, testbench improved to send a frame (crc still missing).
 
 
 
//
 
// Revision 1.5  2002/12/26 16:00:29  mohor
 
// Revision 1.5  2002/12/26 16:00:29  mohor
 
// Testbench define file added. Clock divider register added.
 
// Testbench define file added. Clock divider register added.
 
//
 
//
 
// Revision 1.4  2002/12/26 01:33:01  mohor
 
// Revision 1.4  2002/12/26 01:33:01  mohor
 
// Tripple sampling supported.
 
// Tripple sampling supported.
Line 83... Line 86... 
reg   [7:0] data_in;
 
reg   [7:0] data_in;
 
wire  [7:0] data_out;
 
wire  [7:0] data_out;
 
reg         cs, rw;
 
reg         cs, rw;
 
reg   [7:0] addr;
 
reg   [7:0] addr;
 
reg         rx;
 
reg         rx;
 
reg         idle;
 
 
 
integer     start_tb;
 
integer     start_tb;
 
 
 
 
 
/* Instantiate can_top module */
 
/* Instantiate can_top module */
 
can_top i_can_top
 
can_top i_can_top
 
(
 
(
Line 96... Line 98... 
  .data_in(data_in),
 
  .data_in(data_in),
 
  .data_out(data_out),
 
  .data_out(data_out),
 
  .cs(cs),
 
  .cs(cs),
 
  .rw(rw),
 
  .rw(rw),
 
  .addr(addr),
 
  .addr(addr),
 
  .rx(rx),
 
  .rx(rx)
 
  .idle(idle)
 
 
 
);
 
);
 
 
 
 
 
 
 
 
 
// Generate clock signal 24 MHz
 
// Generate clock signal 24 MHz
 
initial
 
initial
Line 117... Line 118... 
  cs = 0;
 
  cs = 0;
 
  rw = 'hz;
 
  rw = 'hz;
 
  addr = 'hz;
 
  addr = 'hz;
 
  rx = 1;
 
  rx = 1;
 
  rst = 1;
 
  rst = 1;
 
  idle = 1;
 
 
 
  #200 rst = 0;
 
  #200 rst = 0;
 
  #200 start_tb = 1;
 
  #200 start_tb = 1;
 
end
 
end
 
 
 
 
 
 
 
 
Line 137... Line 137... 
  write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
  write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
 
 
 
 
  #10;
 
  #10;
 
  repeat (1000) @ (posedge clk);
 
  repeat (1000) @ (posedge clk);
 
 
 
 
 
 
 
  /* Switch-off reset mode */
 
 
 
  write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
 
 
 
 
 
 
 
  repeat (BRP) @ (posedge clk);   // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
 
 
 
                                  // This difference is resynchronized later.
 
 
 
 
 
//  test_synchronization;
 
//  test_synchronization;
 
  repeat (2) @ (posedge clk);   // So we are not synchronized to anything
 
 
 
  send_frame(1, 29'h12345678, 1); // mode, id, length
 
  repeat (7) send_bit(1);         // Sending EOF
 
 
 
 
 
 
 
 
 
 
 
  send_frame(1, 29'h00075678, 1); // mode, id, length
 
 
 
 
 
 
 
 
 
  repeat (50000) @ (posedge clk);
 
  repeat (50000) @ (posedge clk);
 
  $display("CAN Testbench finished.");
 
  $display("CAN Testbench finished.");
 
  $stop;
 
  $stop;
Line 174... Line 183... 
 
 
 
 
 
 
 
 
task test_synchronization;
 
task test_synchronization;
 
  begin
 
  begin
 
    // Hard synchronization
 
    // Hard synchronization
 
    repeat (2) @ (posedge clk);   // So we are not synchronized to anything
 
 
 
    #1 rx=0;
 
    #1 rx=0;
 
    repeat (2*BRP) @ (posedge clk);
 
    repeat (2*BRP) @ (posedge clk);
 
    #1 idle = 0;
 
//    #1 idle = 0;
 
    repeat (8*BRP) @ (posedge clk);
 
    repeat (8*BRP) @ (posedge clk);
 
    #1 rx=1;
 
    #1 rx=1;
 
    repeat (10*BRP) @ (posedge clk);
 
    repeat (10*BRP) @ (posedge clk);
 
 
 
 
 
    // Resynchronization on time
 
    // Resynchronization on time
 
    #1 rx=0;
 
    #1 rx=0;
 
    repeat (10*BRP) @ (posedge clk);
 
    repeat (10*BRP) @ (posedge clk);
 
    #1 rx=1;
 
    #1 rx=1;
 
    idle = 0;
 
//    idle = 0;
 
    repeat (10*BRP) @ (posedge clk);
 
    repeat (10*BRP) @ (posedge clk);
 
 
 
 
 
    // Resynchronization late
 
    // Resynchronization late
 
    repeat (BRP) @ (posedge clk);
 
    repeat (BRP) @ (posedge clk);
 
    repeat (BRP) @ (posedge clk);
 
    repeat (BRP) @ (posedge clk);
 
    #1 rx=0;
 
    #1 rx=0;
 
    repeat (10*BRP) @ (posedge clk);
 
    repeat (10*BRP) @ (posedge clk);
 
    #1 rx=1;
 
    #1 rx=1;
 
    idle = 0;
 
//    idle = 0;
 
 
 
 
 
    // Resynchronization early
 
    // Resynchronization early
 
    repeat (8*BRP) @ (posedge clk);   // two frames too early
 
    repeat (8*BRP) @ (posedge clk);   // two frames too early
 
    #1 rx=0;
 
    #1 rx=0;
 
    repeat (10*BRP) @ (posedge clk);
 
    repeat (10*BRP) @ (posedge clk);
 
    #1 rx=1;
 
    #1 rx=1;
 
    idle = 0;
 
//    idle = 0;
 
    repeat (10*BRP) @ (posedge clk);
 
    repeat (10*BRP) @ (posedge clk);
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
 
 
 
Line 214... Line 222... 
  input bit;
 
  input bit;
 
  integer cnt;
 
  integer cnt;
 
  begin
 
  begin
 
    #1 rx=bit;
 
    #1 rx=bit;
 
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
 
    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);
 
    idle=0;
 
//    idle=0;
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
 
 
 
 
task send_frame;
 
task send_frame;
Line 302... Line 310... 
/* State machine monitor (btl) */
 
/* State machine monitor (btl) */
 
always @ (posedge clk)
 
always @ (posedge clk)
 
begin
 
begin
 
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
 
  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |
 
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
 
     can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)
 
     $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance", $time);
 
    begin
 
 
 
      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);
 
 
 
      #1000;
 
 
 
      $stop;
 
 
 
    end
 
 
 
 
 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
 
  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |
 
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
 
     can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)
 
     $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance", $time);
 
    begin
 
 
 
      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);
 
 
 
      #1000;
 
 
 
      $stop;
 
end
 
end
 
 
 
end
 
 
 
 
 
 
 
/* stuff_error monitor (bsp)
 
 
 
always @ (posedge clk)
 
 
 
begin
 
 
 
  if(can_testbench.i_can_top.i_can_bsp.stuff_error)
 
 
 
    begin
 
 
 
      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);
 
 
 
      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop
 
 
 
    end
 
 
 
end
 
 
 
*/
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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