| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2003/01/08 02:09:43 mohor
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// Acceptance filter added.
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//
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// Revision 1.7 2002/12/28 04:13:53 mohor
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// Revision 1.7 2002/12/28 04:13:53 mohor
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// Backup version.
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// Backup version.
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//
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//
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// Revision 1.6 2002/12/27 00:12:48 mohor
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// Revision 1.6 2002/12/27 00:12:48 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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// Header changed, testbench improved to send a frame (crc still missing).
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| Line 90... |
Line 93... |
wire [7:0] data_out;
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wire [7:0] data_out;
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reg cs, rw;
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reg cs, rw;
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reg [7:0] addr;
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reg [7:0] addr;
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reg rx;
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reg rx;
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integer start_tb;
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integer start_tb;
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reg [7:0] tmp_data;
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// Instantiate can_top module
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// Instantiate can_top module
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can_top i_can_top
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can_top i_can_top
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(
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(
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.clk(clk),
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.clk(clk),
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| Line 137... |
Line 141... |
write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
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write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
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// Set bus timing register 1
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// Set bus timing register 1
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write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
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// Set Clock Divider register
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// Set Clock Divider register
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write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
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write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
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// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
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// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
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| Line 186... |
Line 192... |
send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
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send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc
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end
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end
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repeat (50000) @ (posedge clk);
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repeat (50000) @ (posedge clk);
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read_register(8'h4);
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read_register(8'h20);
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read_register(8'h21);
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read_register(8'h22);
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read_register(8'h23);
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read_register(8'h24);
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read_register(8'h25);
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$display("CAN Testbench finished.");
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$display("CAN Testbench finished.");
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$stop;
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$stop;
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end
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end
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task read_register;
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input [7:0] reg_addr;
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begin
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@ (posedge clk);
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#1;
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addr = reg_addr;
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cs = 1;
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rw = 1;
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@ (posedge clk);
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$display("(%0t) Reading register [0x%0x] = 0x%0x", $time, addr, data_out);
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#1;
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addr = 'hz;
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cs = 0;
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rw = 'hz;
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end
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endtask
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task write_register;
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task write_register;
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input [7:0] reg_addr;
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input [7:0] reg_addr;
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input [7:0] reg_data;
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input [7:0] reg_data;
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begin
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begin
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