| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.17 2003/01/31 01:13:31 mohor
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// backup.
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//
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// Revision 1.16 2003/01/16 13:36:14 mohor
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// Revision 1.16 2003/01/16 13:36:14 mohor
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// Form error supported. When receiving messages, last bit of the end-of-frame
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// Form error supported. When receiving messages, last bit of the end-of-frame
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// does not generate form error. Receiver goes to the idle mode one bit sooner.
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// does not generate form error. Receiver goes to the idle mode one bit sooner.
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// (CAN specification ver 2.0, part B, page 57).
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// (CAN specification ver 2.0, part B, page 57).
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//
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//
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| Line 212... |
Line 215... |
end
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end
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else
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else
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begin
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begin
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// Set Acceptance Code and Acceptance Mask registers
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// Set Acceptance Code and Acceptance Mask registers
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// write_register(8'd4, 8'ha6); // acceptance code
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// write_register(8'd4, 8'ha6); // acceptance code
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write_register(8'd4, 8'h08); // acceptance code
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write_register(8'd4, 8'he8); // acceptance code
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write_register(8'd5, 8'h00); // acceptance mask
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write_register(8'd5, 8'h0f); // acceptance mask
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end
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end
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#10;
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#10;
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repeat (1000) @ (posedge clk);
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repeat (1000) @ (posedge clk);
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| Line 247... |
Line 250... |
// test_full_fifo; // test currently switched off
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// test_full_fifo; // test currently switched off
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send_frame; // test currently switched on
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send_frame; // test currently switched on
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end
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end
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$display("CAN Testbench finished !");
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$display("CAN Testbench finished !");
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$stop;
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$stop;
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end
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end
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| Line 277... |
Line 279... |
write_register(8'd27, 8'ha9);
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write_register(8'd27, 8'ha9);
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write_register(8'd28, 8'h87);
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write_register(8'd28, 8'h87);
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end
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end
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else
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else
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begin
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begin
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write_register(8'd10, 8'h12); // Writing ID[10:3] = 0x12
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write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea
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write_register(8'd11, 8'h04); // Writing ID[3:0] = 0x0, rtr = 0, length = 4
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write_register(8'd11, 8'h18); // Writing ID[3:0] = 0x0, rtr = 1, length = 8
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write_register(8'd12, 8'h56); // data byte 1
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write_register(8'd12, 8'h56); // data byte 1
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write_register(8'd13, 8'h78); // data byte 2
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write_register(8'd13, 8'h78); // data byte 2
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write_register(8'd14, 8'h9a); // data byte 3
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write_register(8'd14, 8'h9a); // data byte 3
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write_register(8'd15, 8'hbc); // data byte 4
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write_register(8'd15, 8'hbc); // data byte 4
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write_register(8'd16, 8'hde); // data byte 5
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write_register(8'd16, 8'hde); // data byte 5
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write_register(8'd17, 8'hf0); // data byte 6
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write_register(8'd17, 8'hf0); // data byte 6
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write_register(8'd18, 8'h0f); // data byte 7
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write_register(8'd18, 8'h0f); // data byte 7
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write_register(8'd19, 8'hed); // data byte 8
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write_register(8'd19, 8'hed); // data byte 8
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end
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end
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fork
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begin
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$display("\n\nStart receiving data from CAN bus");
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receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
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receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
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end
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begin
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tx_request;
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end
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begin
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// Transmitting acknowledge
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wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
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rx = 0;
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wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim);
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rx = 1;
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end
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join
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read_receive_buffer;
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release_rx_buffer;
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release_rx_buffer;
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read_receive_buffer;
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release_rx_buffer;
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read_receive_buffer;
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release_rx_buffer;
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read_receive_buffer;
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release_rx_buffer;
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read_receive_buffer;
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#200000;
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read_receive_buffer;
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end
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end
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endtask
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endtask
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| Line 665... |
Line 708... |
repeat (2) @ (posedge clk); // Time to decrement all the counters
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repeat (2) @ (posedge clk); // Time to decrement all the counters
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end
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end
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endtask
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endtask
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task tx_request;
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begin
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write_register(8'd1, 8'h1);
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$display("(%0t) Tx requested.", $time);
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repeat (2) @ (posedge clk); // Time to decrement all the counters, etc.
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end
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endtask
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task test_synchronization;
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task test_synchronization;
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begin
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begin
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// Hard synchronization
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// Hard synchronization
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#1 rx=0;
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#1 rx=0;
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repeat (2*BRP) @ (posedge clk);
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repeat (2*BRP) @ (posedge clk);
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| Line 713... |
Line 765... |
input mode;
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input mode;
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input remote_trans_req;
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input remote_trans_req;
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input [28:0] id;
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input [28:0] id;
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input [3:0] length;
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input [3:0] length;
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input [14:0] crc;
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input [14:0] crc;
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reg [117:0] data;
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reg previous_bit;
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reg stuff;
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reg tmp;
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reg arbitration_lost;
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integer pointer;
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integer pointer;
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integer cnt;
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integer cnt;
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integer total_bits;
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integer total_bits;
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integer stuff_cnt;
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integer stuff_cnt;
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reg [117:0] data;
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reg previous_bit;
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reg stuff;
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begin
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begin
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stuff_cnt = 1;
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stuff_cnt = 1;
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stuff = 0;
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stuff = 0;
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| Line 764... |
Line 819... |
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// This is how many bits we need to shift
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// This is how many bits we need to shift
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total_bits = pointer;
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total_bits = pointer;
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// Waiting until previous msg is finished before sending another one
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// Waiting until previous msg is finished before sending another one
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wait (~can_testbench.i_can_top.i_can_bsp.error_frame & ~can_testbench.i_can_top.i_can_bsp.rx_inter);
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wait (~can_testbench.i_can_top.i_can_bsp.error_frame & ~can_testbench.i_can_top.i_can_bsp.rx_inter & ~can_testbench.i_can_top.i_can_bsp.tx_state);
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arbitration_lost = 0;
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send_bit(0); // SOF
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send_bit(0); // SOF
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previous_bit = 0;
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previous_bit = 0;
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fork
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begin
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while (~arbitration_lost)
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begin
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for (cnt=0; cnt<=total_bits; cnt=cnt+1)
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for (cnt=0; cnt<=total_bits; cnt=cnt+1)
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begin
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begin
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if (stuff_cnt == 5)
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if (stuff_cnt == 5)
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begin
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begin
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stuff_cnt = 1;
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stuff_cnt = 1;
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total_bits = total_bits + 1;
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total_bits = total_bits + 1;
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stuff = 1;
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stuff = 1;
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tmp = ~data[pointer+1];
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send_bit(~data[pointer+1]);
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send_bit(~data[pointer+1]);
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previous_bit = ~data[pointer+1];
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previous_bit = ~data[pointer+1];
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end
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end
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else
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else
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begin
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begin
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| Line 787... |
Line 849... |
stuff_cnt <= stuff_cnt + 1;
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stuff_cnt <= stuff_cnt + 1;
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else
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else
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stuff_cnt <= 1;
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stuff_cnt <= 1;
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stuff = 0;
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stuff = 0;
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tmp = data[pointer];
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send_bit(data[pointer]);
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send_bit(data[pointer]);
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previous_bit = data[pointer];
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previous_bit = data[pointer];
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pointer = pointer - 1;
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pointer = pointer - 1;
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end
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end
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if (arbitration_lost)
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cnt=total_bits+1; // Exit the for loop
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end
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end
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arbitration_lost = 1; // At the end we exit the while loop
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// Nothing send after the data (just recessive bit)
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// Nothing send after the data (just recessive bit)
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repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
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repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
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end
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end
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end
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begin
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while (~arbitration_lost)
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begin
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#1 wait (can_testbench.i_can_top.sample_point);
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// $display("(%0t)", $time);
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if (mode)
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begin
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if (cnt<32 & tmp & (~rx_and_tx))
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begin
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arbitration_lost = 1;
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rx = 1; // Only recessive is send from now on.
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end
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end
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else
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begin
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if (cnt<12 & tmp & (~rx_and_tx))
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begin
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arbitration_lost = 1;
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rx = 1; // Only recessive is send from now on.
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end
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end
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end
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end
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join
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// // Nothing send after the data (just recessive bit)
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// repeat (13) send_bit(1); // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3
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end
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endtask
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endtask
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// State machine monitor (btl)
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// State machine monitor (btl)
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