| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.20 2003/02/09 02:24:11 mohor
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// Bosch license warning added. Error counters finished. Overload frames
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// still need to be fixed.
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//
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// Revision 1.19 2003/02/04 17:24:33 mohor
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// Revision 1.19 2003/02/04 17:24:33 mohor
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// Backup.
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// Backup.
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//
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//
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// Revision 1.18 2003/02/04 14:34:45 mohor
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// Revision 1.18 2003/02/04 14:34:45 mohor
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// *** empty log message ***
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// *** empty log message ***
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| Line 277... |
Line 281... |
end
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end
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task manual_frame; // Testbench sends a frame
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task manual_frame; // Testbench sends a frame
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begin
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begin
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begin
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/*
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/*
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begin
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$display("\n\nTestbench sends a frame bit by bit");
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$display("\n\nTestbench sends a frame bit by bit");
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send_bit(0); // SOF
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send_bit(0); // SOF
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send_bit(1); // ID
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send_bit(1); // ID
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send_bit(1); // ID
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send_bit(1); // ID
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send_bit(1); // ID
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send_bit(1); // ID
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| Line 345... |
Line 349... |
send_bit(1); // IDLE // delimiter
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send_bit(1); // IDLE // delimiter
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send_bit(1); // IDLE // delimiter
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send_bit(1); // IDLE // delimiter
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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end
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*/
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*/
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// tx_bypassed=1;
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write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
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write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
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write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
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write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
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write_register(8'd12, 8'h00); // data byte 1
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write_register(8'd12, 8'h00); // data byte 1
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write_register(8'd13, 8'h00); // data byte 2
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write_register(8'd13, 8'h00); // data byte 2
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| Line 357... |
Line 365... |
write_register(8'd15, 8'h00); // data byte 4
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write_register(8'd15, 8'h00); // data byte 4
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write_register(8'd16, 8'h00); // data byte 5
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write_register(8'd16, 8'h00); // data byte 5
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write_register(8'd17, 8'h00); // data byte 6
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write_register(8'd17, 8'h00); // data byte 6
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write_register(8'd18, 8'h00); // data byte 7
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write_register(8'd18, 8'h00); // data byte 7
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write_register(8'd19, 8'h00); // data byte 8
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write_register(8'd19, 8'h00); // data byte 8
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end
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// tx_bypassed=1;
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fork
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fork
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begin
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begin
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tx_request;
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tx_request;
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end
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end
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| Line 414... |
Line 418... |
send_bit(1); // EOF
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send_bit(1); // EOF
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send_bit(1); // EOF
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send_bit(1); // EOF
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send_bit(1); // EOF
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send_bit(1); // EOF
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send_bit(1); // EOF
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send_bit(1); // EOF
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// tx_bypassed=1;
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// tx_bypassed=1;
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send_bit(0); // INTER
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER
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send_bit(1); // INTER
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send_bit(1); // INTER
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send_bit(0); // IDLE
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send_bit(1); // INTER
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send_bit(1); // INTER overload
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send_bit(1); // IDLE
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(1); // INTER overload
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send_bit(0); // INTER waiting for recessive
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send_bit(0); // INTER waiting for recessive
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send_bit(0); // INTER waiting for recessive
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send_bit(0); // INTER waiting for recessive
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // INTER overload delim
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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send_bit(1); // IDLE
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|
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end
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end
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