URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 29 and 31

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Rev 29	Rev 31
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.21 2003/02/09 18:40:23 mohor`
	`// Overload fixed. Hard synchronization also enabled at the last bit of`
	`// interframe.`
	`//`
`// Revision 1.20 2003/02/09 02:24:11 mohor`	`// Revision 1.20 2003/02/09 02:24:11 mohor`
`// Bosch license warning added. Error counters finished. Overload frames`	`// Bosch license warning added. Error counters finished. Overload frames`
`// still need to be fixed.`	`// still need to be fixed.`
`//`	`//`
`// Revision 1.19 2003/02/04 17:24:33 mohor`	`// Revision 1.19 2003/02/04 17:24:33 mohor`
Line 70...	Line 74...
`//`	`//`
`// Revision 1.15 2003/01/15 21:05:06 mohor`	`// Revision 1.15 2003/01/15 21:05:06 mohor`
`// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).`	`// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).`
`//`	`//`
`// Revision 1.14 2003/01/15 14:40:16 mohor`	`// Revision 1.14 2003/01/15 14:40:16 mohor`
`// RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.`	`// RX state machine fixed to receive "remote request" frames correctly. No`
	`// data bytes are written to fifo when such frames are received.`
`//`	`//`
`// Revision 1.13 2003/01/15 13:16:42 mohor`	`// Revision 1.13 2003/01/15 13:16:42 mohor`
`// When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.`	`// When a frame with "remote request" is received, no data is stored to`
	`// fifo, just the frame information (identifier, ...). Data length that`
	`// is stored is the received data length and not the actual data length`
	`// that is stored to fifo.`
`//`	`//`
`// Revision 1.12 2003/01/14 17:25:03 mohor`	`// Revision 1.12 2003/01/14 17:25:03 mohor`
`// Addresses corrected to decimal values (previously hex).`	`// Addresses corrected to decimal values (previously hex).`
`//`	`//`
`// Revision 1.11 2003/01/14 12:19:29 mohor`	`// Revision 1.11 2003/01/14 12:19:29 mohor`
Line 129...	Line 137...
`parameter Tp = 1;`	`parameter Tp = 1;`
parameter BRP = 2*(`CAN_TIMING0_BRP + 1);	parameter BRP = 2*(`CAN_TIMING0_BRP + 1);



	`reg wb_clk_i;`
	`reg wb_rst_i;`
	`reg [7:0] wb_dat_i;`
	`wire [7:0] wb_dat_o;`
	`reg wb_cyc_i;`
	`reg wb_stb_i;`

	`reg wb_we_i;`
	`reg [7:0] wb_adr_i;`
`reg clk;`	`reg clk;`
`reg rst;`
`reg [7:0] data_in;`
`wire [7:0] data_out;`
`reg cs, rw;`
`reg [7:0] addr;`
`reg rx;`	`reg rx;`
`wire tx;`	`wire tx;`
`wire tx_oen;`	`wire tx_oen;`
	`wire wb_ack_o;`

`wire tx_3st;`	`wire tx_3st;`
`wire rx_and_tx;`	`wire rx_and_tx;`

`integer start_tb;`	`integer start_tb;`
`reg [7:0] tmp_data;`	`reg [7:0] tmp_data;`
Line 150...	Line 164...


`// Instantiate can_top module`	`// Instantiate can_top module`
`can_top i_can_top`	`can_top i_can_top`
`(`	`(`
	`.wb_clk_i(wb_clk_i),`
	`.wb_rst_i(wb_rst_i),`
	`.wb_dat_i(wb_dat_i),`
	`.wb_dat_o(wb_dat_o),`
	`.wb_cyc_i(wb_cyc_i),`
	`.wb_stb_i(wb_stb_i),`
	`.wb_we_i(wb_we_i),`
	`.wb_adr_i(wb_adr_i),`
	`.wb_ack_o(wb_ack_o),`
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`
`.data_in(data_in),`
`.data_out(data_out),`
`.cs(cs),`
`.rw(rw),`
`.addr(addr),`
`.rx(rx_and_tx),`	`.rx(rx_and_tx),`
`.tx(tx),`	`.tx(tx),`
`.tx_oen(tx_oen)`	`.tx_oen(tx_oen)`
`);`	`);`

`assign tx_3st = tx_oen? 1'bz : tx;`	`assign tx_3st = tx_oen? 1'bz : tx;`


	`// Generate wishbone clock signal 10 MHz`
	`initial`
	`begin`
	`wb_clk_i=0;`
	`forever #50 wb_clk_i = ~wb_clk_i;`
	`end`


`// Generate clock signal 24 MHz`	`// Generate clock signal 24 MHz`
`initial`	`initial`
`begin`	`begin`
`clk=0;`	`clk=0;`
`forever #20 clk = ~clk;`	`forever #20 clk = ~clk;`
`end`	`end`


`initial`	`initial`
`begin`	`begin`
`start_tb = 0;`	`start_tb = 0;`
`data_in = 'hz;`	`wb_dat_i = 'hz;`
`cs = 0;`	`wb_cyc_i = 0;`
`rw = 'hz;`	`wb_stb_i = 0;`
`addr = 'hz;`	`wb_we_i = 'hz;`
	`wb_adr_i = 'hz;`
`rx = 1;`	`rx = 1;`
`rst = 1;`	`wb_rst_i = 1;`
`#200 rst = 0;`	`#200 wb_rst_i = 0;`
`#200 initialize_fifo;`	`#200 initialize_fifo;`
`#200 start_tb = 1;`	`#200 start_tb = 1;`
`tx_bypassed = 0;`	`tx_bypassed = 0;`
`end`	`end`

Line 238...	Line 265...
`end`	`end`
`else`	`else`
`begin`	`begin`
`// Set Acceptance Code and Acceptance Mask registers`	`// Set Acceptance Code and Acceptance Mask registers`
`// write_register(8'd4, 8'ha6); // acceptance code`	`// write_register(8'd4, 8'ha6); // acceptance code`
`write_register(8'd4, 8'he8); // acceptance code`	`write_register(8'd4, 8'h08); // acceptance code`
`write_register(8'd5, 8'h0f); // acceptance mask`	`write_register(8'd5, 8'h0f); // acceptance mask`
`end`	`end`

`#10;`	`#10;`
`repeat (1000) @ (posedge clk);`	`repeat (1000) @ (posedge clk);`
Line 268...	Line 295...
`// send_frame_ext; // test currently switched off`	`// send_frame_ext; // test currently switched off`
`end`	`end`
`else`	`else`
`begin`	`begin`
`// test_empty_fifo; // test currently switched off`	`// test_empty_fifo; // test currently switched off`
`// test_full_fifo; // test currently switched off`	`test_full_fifo; // test currently switched on`
`// send_frame; // test currently switched off`	`// send_frame; // test currently switched off`
`manual_frame; // test currently switched on`	`// manual_frame; // test currently switched off`
`end`	`end`


`$display("CAN Testbench finished !");`	`$display("CAN Testbench finished !");`
`$stop;`	`$stop;`
Line 373...	Line 400...
`tx_request;`	`tx_request;`
`end`	`end`

`begin`	`begin`
`#520;`	`#520;`

	`repeat (16)`
	`begin`
	`send_bit(0); // SOF`
	`send_bit(1); // ID`
	`send_bit(1); // ID`
	`send_bit(1); // ID`
	`send_bit(0); // ID`
	`send_bit(1); // ID`
	`send_bit(0); // ID`
	`send_bit(0); // ID`
	`send_bit(0); // ID`
	`send_bit(1); // ID`
	`send_bit(0); // ID`
	`send_bit(1); // ID`
	`send_bit(1); // RTR`
	`send_bit(0); // IDE`
	`send_bit(0); // r0`
	`send_bit(0); // DLC`
	`send_bit(1); // DLC`
	`send_bit(1); // DLC`
	`send_bit(1); // DLC`
	`send_bit(1); // CRC`
	`send_bit(0); // CRC`
	`send_bit(0); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(0); // CRC`
	`send_bit(1); // CRC`
	`send_bit(0); // CRC`
	`send_bit(0); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC DELIM`
	`send_bit(1); // ACK ack error`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // INTER`
	`send_bit(1); // INTER`
	`send_bit(1); // INTER`
	`end // repeat`

	`repeat (20)`
	`begin`
	`send_bit(0); // SOF`
	`send_bit(1); // ID`
	`send_bit(1); // ID`
	`send_bit(1); // ID`
	`send_bit(0); // ID`
	`send_bit(1); // ID`
	`send_bit(0); // ID`
	`send_bit(0); // ID`
	`send_bit(0); // ID`
	`send_bit(1); // ID`
	`send_bit(0); // ID`
	`send_bit(1); // ID`
	`send_bit(1); // RTR`
	`send_bit(0); // IDE`
	`send_bit(0); // r0`
	`send_bit(0); // DLC`
	`send_bit(1); // DLC`
	`send_bit(1); // DLC`
	`send_bit(1); // DLC`
	`send_bit(1); // CRC`
	`send_bit(0); // CRC`
	`send_bit(0); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(0); // CRC`
	`send_bit(1); // CRC`
	`send_bit(0); // CRC`
	`send_bit(0); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC`
	`send_bit(1); // CRC DELIM`
	`send_bit(1); // ACK ack error`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(0); // ERROR`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // ERROR DELIM`
	`send_bit(1); // INTER`
	`send_bit(1); // INTER`
	`send_bit(1); // INTER`
	`send_bit(1); // SUSPEND`
	`send_bit(1); // SUSPEND`
	`send_bit(1); // SUSPEND`
	`send_bit(1); // SUSPEND`
	`send_bit(1); // SUSPEND`
	`send_bit(1); // SUSPEND`
	`send_bit(1); // SUSPEND`
	`send_bit(1); // SUSPEND`
	`end // repeat`

	`repeat (20)`
	`begin`
`send_bit(0); // SOF`	`send_bit(0); // SOF`
`send_bit(1); // ID`	`send_bit(1); // ID`
`send_bit(1); // ID`	`send_bit(1); // ID`
`send_bit(1); // ID`	`send_bit(1); // ID`
`send_bit(0); // ID`	`send_bit(0); // ID`
Line 417...	Line 569...
`send_bit(1); // EOF`	`send_bit(1); // EOF`
`send_bit(1); // EOF`	`send_bit(1); // EOF`
`send_bit(1); // EOF`	`send_bit(1); // EOF`
`send_bit(1); // EOF`	`send_bit(1); // EOF`
`send_bit(1); // EOF`	`send_bit(1); // EOF`
`// tx_bypassed=1;`
`send_bit(0); // INTER`
`send_bit(1); // INTER overload`
`send_bit(1); // INTER overload`
`send_bit(1); // INTER overload`
`send_bit(1); // INTER overload`
`send_bit(1); // INTER overload`
`send_bit(1); // INTER overload`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER`	`send_bit(1); // INTER`
`send_bit(0); // IDLE`	`send_bit(1); // INTER`
`send_bit(1); // INTER overload`	`send_bit(1); // INTER`
`send_bit(1); // INTER overload`	`end // repeat`
`send_bit(1); // INTER overload`
`send_bit(1); // INTER overload`	`repeat (128 * 11)`
`send_bit(1); // INTER overload`	`begin`
`send_bit(1); // INTER overload`	`send_bit(1);`
`send_bit(0); // INTER waiting for recessive`	`end // repeat`
`send_bit(0); // INTER waiting for recessive`
`send_bit(0); // INTER waiting for recessive`	`tx_request;`
`send_bit(0); // INTER waiting for recessive`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // INTER overload delim`
`send_bit(1); // IDLE`
`send_bit(1); // IDLE`
`send_bit(1); // IDLE`

`end`	`end`


`join`	`join`
Line 473...	Line 600...

`read_receive_buffer;`	`read_receive_buffer;`
`release_rx_buffer;`	`release_rx_buffer;`
`read_receive_buffer;`	`read_receive_buffer;`

`#200000;`	`#4000000;`

`end`	`end`
`endtask`	`endtask`


Line 867...	Line 994...

`task read_register;`	`task read_register;`
`input [7:0] reg_addr;`	`input [7:0] reg_addr;`

`begin`	`begin`
`@ (posedge clk);`	`@ (posedge wb_clk_i);`
`#1;`	`#1;`
`addr = reg_addr;`	`wb_adr_i = reg_addr;`
`cs = 1;`	`wb_cyc_i = 1;`
`rw = 1;`	`wb_stb_i = 1;`
`@ (posedge clk);`	`wb_we_i = 0;`
`$display("(%0t) Reading register [%0d] = 0x%0x", $time, addr, data_out);`	`wait (wb_ack_o);`
	`$display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o);`
	`@ (posedge wb_clk_i);`
`#1;`	`#1;`
`addr = 'hz;`	`wb_adr_i = 'hz;`
`cs = 0;`	`wb_cyc_i = 0;`
`rw = 'hz;`	`wb_stb_i = 0;`
	`wb_we_i = 'hz;`
`end`	`end`
`endtask`	`endtask`


`task write_register;`	`task write_register;`
`input [7:0] reg_addr;`	`input [7:0] reg_addr;`
`input [7:0] reg_data;`	`input [7:0] reg_data;`

`begin`	`begin`
`@ (posedge clk);`	`@ (posedge wb_clk_i);`
`#1;`	`#1;`
`addr = reg_addr;`	`wb_adr_i = reg_addr;`
`data_in = reg_data;`	`wb_dat_i = reg_data;`
`cs = 1;`	`wb_cyc_i = 1;`
`rw = 0;`	`wb_stb_i = 1;`
`@ (posedge clk);`	`wb_we_i = 1;`
	`wait (wb_ack_o);`
	`@ (posedge wb_clk_i);`
`#1;`	`#1;`
`addr = 'hz;`	`wb_adr_i = 'hz;`
`data_in = 'hz;`	`wb_dat_i = 'hz;`
`cs = 0;`	`wb_cyc_i = 0;`
`rw = 'hz;`	`wb_stb_i = 0;`
	`wb_we_i = 'hz;`
`end`	`end`
`endtask`	`endtask`


`task read_receive_buffer;`	`task read_receive_buffer;`
Line 928...	Line 1061...

`task release_rx_buffer;`	`task release_rx_buffer;`
`begin`	`begin`
`write_register(8'd1, 8'h4);`	`write_register(8'd1, 8'h4);`
`$display("(%0t) Rx buffer released.", $time);`	`$display("(%0t) Rx buffer released.", $time);`
`repeat (2) @ (posedge clk); // Time to decrement all the counters`
`end`	`end`
`endtask`	`endtask`


`task tx_request;`	`task tx_request;`
`begin`	`begin`
`write_register(8'd1, 8'h1);`	`write_register(8'd1, 8'h1);`
`$display("(%0t) Tx requested.", $time);`	`$display("(%0t) Tx requested.", $time);`
`repeat (2) @ (posedge clk); // Time to decrement all the counters, etc.`
`end`	`end`
`endtask`	`endtask`


`task test_synchronization;`	`task test_synchronization;`

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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 29 and 31