| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.23 2003/02/12 14:28:30 mohor
|
|
// Errors monitoring improved. arbitration_lost improved.
|
|
//
|
// Revision 1.22 2003/02/11 00:57:19 mohor
|
// Revision 1.22 2003/02/11 00:57:19 mohor
|
// Wishbone interface added.
|
// Wishbone interface added.
|
//
|
//
|
// Revision 1.21 2003/02/09 18:40:23 mohor
|
// Revision 1.21 2003/02/09 18:40:23 mohor
|
// Overload fixed. Hard synchronization also enabled at the last bit of
|
// Overload fixed. Hard synchronization also enabled at the last bit of
|
| Line 154... |
Line 157... |
reg clk;
|
reg clk;
|
reg rx;
|
reg rx;
|
wire tx;
|
wire tx;
|
wire tx_oen;
|
wire tx_oen;
|
wire wb_ack_o;
|
wire wb_ack_o;
|
|
wire irq;
|
|
|
wire tx_3st;
|
wire tx_3st;
|
wire rx_and_tx;
|
wire rx_and_tx;
|
|
|
integer start_tb;
|
integer start_tb;
|
| Line 180... |
Line 184... |
.wb_adr_i(wb_adr_i),
|
.wb_adr_i(wb_adr_i),
|
.wb_ack_o(wb_ack_o),
|
.wb_ack_o(wb_ack_o),
|
.clk(clk),
|
.clk(clk),
|
.rx(rx_and_tx),
|
.rx(rx_and_tx),
|
.tx(tx),
|
.tx(tx),
|
.tx_oen(tx_oen)
|
.tx_oen(tx_oen),
|
|
.irq(irq)
|
);
|
);
|
|
|
assign tx_3st = tx_oen? 1'bz : tx;
|
assign tx_3st = tx_oen? 1'bz : tx;
|
|
|
|
|
// Generate wishbone clock signal 10 MHz
|
// Generate wishbone clock signal 10 MHz FIX ME
|
initial
|
initial
|
begin
|
begin
|
wb_clk_i=0;
|
wb_clk_i=0;
|
forever #50 wb_clk_i = ~wb_clk_i;
|
forever #20 wb_clk_i = ~wb_clk_i;
|
end
|
end
|
|
|
|
|
// Generate clock signal 24 MHz
|
// Generate clock signal 24 MHz FIX ME
|
initial
|
initial
|
begin
|
begin
|
clk=0;
|
clk=0;
|
forever #20 clk = ~clk;
|
forever #20 clk = ~clk;
|
end
|
end
|
| Line 249... |
Line 254... |
|
|
// Set bus timing register 1
|
// Set bus timing register 1
|
write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
|
write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
|
|
|
|
|
|
|
// Set Clock Divider register
|
// Set Clock Divider register
|
write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
|
write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
|
|
|
// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
|
// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
|
| Line 301... |
Line 305... |
end
|
end
|
else
|
else
|
begin
|
begin
|
// test_empty_fifo; // test currently switched off
|
// test_empty_fifo; // test currently switched off
|
// test_full_fifo; // test currently switched off
|
// test_full_fifo; // test currently switched off
|
send_frame; // test currently switched on
|
send_frame; // test currently switched off
|
|
// bus_off_test; // test currently switched off
|
// manual_frame; // test currently switched off
|
// manual_frame; // test currently switched off
|
|
// forced_bus_off; // test currently switched on
|
end
|
end
|
|
|
|
|
$display("CAN Testbench finished !");
|
$display("CAN Testbench finished !");
|
$stop;
|
$stop;
|
end
|
end
|
|
|
|
|
task manual_frame; // Testbench sends a frame
|
task forced_bus_off; // Forcing bus-off by writinf to tx_err_cnt register
|
begin
|
begin
|
/*
|
|
begin
|
|
|
|
$display("\n\nTestbench sends a frame bit by bit");
|
// Switch-on reset mode
|
send_bit(0); // SOF
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
send_bit(1); // ID
|
|
send_bit(1); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(0); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(1); // RTR
|
|
send_bit(0); // IDE
|
|
send_bit(0); // r0
|
|
send_bit(0); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(0); // DLC
|
|
send_bit(0); // DLC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC // error
|
|
send_bit(1); // CRC DELIM
|
|
send_bit(0); // ACK
|
|
send_bit(1); // ACK DELIM
|
|
send_bit(0); // EOF // error comes here
|
|
send_bit(0); // EOF // error comes here
|
|
|
|
//tx_bypassed=1;
|
|
send_bit(0); // EOF // error comes here
|
|
//tx_bypassed=0;
|
|
|
|
send_bit(0); // EOF // error comes here
|
|
send_bit(0); // EOF // error comes here
|
|
send_bit(0); // EOF // error comes here
|
|
send_bit(1); // EOF // delimiter
|
|
send_bit(1); // INTER // delimiter
|
|
send_bit(1); // INTER // delimiter
|
|
send_bit(1); // INTER // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(0); // IDLE // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(1); // IDLE // delimiter
|
|
send_bit(1); // IDLE
|
|
send_bit(1); // IDLE
|
|
send_bit(1); // IDLE
|
|
|
|
end
|
// Set Clock Divider register
|
*/
|
write_register(8'd31, {1'b1, 7'h0}); // Setting the extended mode (not normal)
|
// tx_bypassed=1;
|
|
|
// Write 255 to tx_err_cnt register - Forcing bus-off
|
|
write_register(8'd15, 255);
|
|
|
|
// Switch-off reset mode
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
|
|
|
// #1000000;
|
|
#2500000;
|
|
|
|
|
|
// Switch-on reset mode
|
|
write_register(8'd0, {7'h0, `CAN_MODE_RESET});
|
|
|
|
// Write 245 to tx_err_cnt register
|
|
write_register(8'd15, 245);
|
|
|
|
// Switch-off reset mode
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
|
|
|
#1000000;
|
|
|
|
|
|
end
|
|
endtask // forced_bus_off
|
|
|
|
|
|
task manual_frame; // Testbench sends a frame
|
|
begin
|
|
|
write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
|
write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
|
write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
|
write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
|
write_register(8'd12, 8'h00); // data byte 1
|
write_register(8'd12, 8'h00); // data byte 1
|
write_register(8'd13, 8'h00); // data byte 2
|
write_register(8'd13, 8'h00); // data byte 2
|
write_register(8'd14, 8'h00); // data byte 3
|
write_register(8'd14, 8'h00); // data byte 3
|
| Line 404... |
Line 372... |
begin
|
begin
|
tx_request;
|
tx_request;
|
end
|
end
|
|
|
begin
|
begin
|
#520;
|
#2000;
|
|
|
repeat (16)
|
repeat (16)
|
begin
|
begin
|
send_bit(0); // SOF
|
send_bit(0); // SOF
|
send_bit(1); // ID
|
send_bit(1); // ID
|
| Line 465... |
Line 433... |
send_bit(1); // INTER
|
send_bit(1); // INTER
|
end // repeat
|
end // repeat
|
|
|
// Node is error passive now.
|
// Node is error passive now.
|
repeat (20)
|
repeat (20)
|
|
|
begin
|
begin
|
send_bit(0); // SOF
|
send_bit(0); // SOF
|
send_bit(1); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
| Line 530... |
Line 499... |
send_bit(1); // SUSPEND
|
send_bit(1); // SUSPEND
|
send_bit(1); // SUSPEND
|
send_bit(1); // SUSPEND
|
end // repeat
|
end // repeat
|
|
|
// Node is bus-off now
|
// Node is bus-off now
|
repeat (20)
|
|
|
#100000;
|
|
|
|
// Switch-off reset mode
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
|
|
|
repeat (128 * 11)
|
|
begin
|
|
send_bit(1);
|
|
end // repeat
|
|
|
|
end
|
|
|
|
|
|
join
|
|
|
|
|
|
|
|
fork
|
|
begin
|
|
tx_request;
|
|
end
|
|
|
|
begin
|
|
#1100;
|
|
|
|
send_bit(1); // To spend some time before transmitter is ready.
|
|
|
|
repeat (1)
|
begin
|
begin
|
send_bit(0); // SOF
|
send_bit(0); // SOF
|
send_bit(1); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
| Line 580... |
Line 577... |
send_bit(1); // EOF
|
send_bit(1); // EOF
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
end // repeat
|
end // repeat
|
|
end
|
|
|
|
join
|
|
|
|
|
|
|
|
|
|
|
|
read_receive_buffer;
|
|
release_rx_buffer;
|
|
|
|
read_receive_buffer;
|
|
release_rx_buffer;
|
|
read_receive_buffer;
|
|
|
|
#4000000;
|
|
|
|
end
|
|
endtask
|
|
|
|
|
|
|
|
task bus_off_test; // Testbench sends a frame
|
|
begin
|
|
|
|
write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8
|
|
write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7
|
|
write_register(8'd12, 8'h00); // data byte 1
|
|
write_register(8'd13, 8'h00); // data byte 2
|
|
write_register(8'd14, 8'h00); // data byte 3
|
|
write_register(8'd15, 8'h00); // data byte 4
|
|
write_register(8'd16, 8'h00); // data byte 5
|
|
write_register(8'd17, 8'h00); // data byte 6
|
|
write_register(8'd18, 8'h00); // data byte 7
|
|
write_register(8'd19, 8'h00); // data byte 8
|
|
|
|
fork
|
|
begin
|
|
tx_request;
|
|
end
|
|
|
|
begin
|
|
#2000;
|
|
|
|
repeat (16)
|
|
begin
|
|
send_bit(0); // SOF
|
|
send_bit(1); // ID
|
|
send_bit(1); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(0); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(1); // RTR
|
|
send_bit(0); // IDE
|
|
send_bit(0); // r0
|
|
send_bit(0); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC DELIM
|
|
send_bit(1); // ACK ack error
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // INTER
|
|
send_bit(1); // INTER
|
|
send_bit(1); // INTER
|
|
end // repeat
|
|
|
|
// Node is error passive now.
|
|
repeat (20)
|
|
|
|
begin
|
|
send_bit(0); // SOF
|
|
send_bit(1); // ID
|
|
send_bit(1); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(0); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(1); // RTR
|
|
send_bit(0); // IDE
|
|
send_bit(0); // r0
|
|
send_bit(0); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC DELIM
|
|
send_bit(1); // ACK ack error
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(0); // ERROR
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // ERROR DELIM
|
|
send_bit(1); // INTER
|
|
send_bit(1); // INTER
|
|
send_bit(1); // INTER
|
|
send_bit(1); // SUSPEND
|
|
send_bit(1); // SUSPEND
|
|
send_bit(1); // SUSPEND
|
|
send_bit(1); // SUSPEND
|
|
send_bit(1); // SUSPEND
|
|
send_bit(1); // SUSPEND
|
|
send_bit(1); // SUSPEND
|
|
send_bit(1); // SUSPEND
|
|
end // repeat
|
|
|
|
// Node is bus-off now
|
|
|
|
#100000;
|
|
|
|
// Switch-off reset mode
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
|
|
repeat (128 * 11)
|
repeat (128 * 11)
|
begin
|
begin
|
send_bit(1);
|
send_bit(1);
|
end // repeat
|
end // repeat
|
|
|
|
end
|
|
|
|
|
|
join
|
|
|
|
|
|
|
|
fork
|
|
begin
|
|
tx_request;
|
end
|
end
|
|
|
|
begin
|
|
#1100;
|
|
|
|
send_bit(1); // To spend some time before transmitter is ready.
|
|
|
|
repeat (1)
|
|
begin
|
|
send_bit(0); // SOF
|
|
send_bit(1); // ID
|
|
send_bit(1); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(0); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(0); // ID
|
|
send_bit(1); // ID
|
|
send_bit(1); // RTR
|
|
send_bit(0); // IDE
|
|
send_bit(0); // r0
|
|
send_bit(0); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // DLC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(0); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC
|
|
send_bit(1); // CRC DELIM
|
|
send_bit(0); // ACK
|
|
send_bit(1); // ACK DELIM
|
|
send_bit(1); // EOF
|
|
send_bit(1); // EOF
|
|
send_bit(1); // EOF
|
|
send_bit(1); // EOF
|
|
send_bit(1); // EOF
|
|
send_bit(1); // EOF
|
|
send_bit(1); // EOF
|
|
send_bit(1); // INTER
|
|
send_bit(1); // INTER
|
|
send_bit(1); // INTER
|
|
end // repeat
|
|
end
|
|
|
join
|
join
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer;
|
|
|
|
|
// #7300000;
|
|
// tx_request;
|
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer;
|
read_receive_buffer;
|
read_receive_buffer;
|
|
|
#4000000;
|
#4000000;
|
|
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
|
|
|
#1000000;
|
|
|
end
|
end
|
endtask
|
endtask // bus_off_test
|
|
|
|
|
|
|
task send_frame; // CAN IP core sends frames
|
task send_frame; // CAN IP core sends frames
|
begin
|
begin
|
| Line 649... |
Line 881... |
write_register(8'd18, 8'h0f); // data byte 7
|
write_register(8'd18, 8'h0f); // data byte 7
|
write_register(8'd19, 8'hed); // data byte 8
|
write_register(8'd19, 8'hed); // data byte 8
|
end
|
end
|
|
|
|
|
|
// Enable irqs (basic mode)
|
|
write_register(8'd0, 8'h1e);
|
|
|
|
|
|
|
fork
|
fork
|
begin
|
begin
|
$display("\n\nStart receiving data from CAN bus");
|
$display("\n\nStart receiving data from CAN bus");
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
|
| Line 690... |
Line 927... |
|
|
#200000;
|
#200000;
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
|
|
|
// Read irq register
|
|
read_register(8'd3);
|
|
#1000;
|
|
|
end
|
end
|
endtask
|
endtask // send_frame
|
|
|
|
|
|
|
task test_empty_fifo;
|
task test_empty_fifo;
|
begin
|
begin
|
| Line 783... |
Line 1024... |
|
|
|
|
|
|
task test_full_fifo;
|
task test_full_fifo;
|
begin
|
begin
|
|
|
|
// Enable irqs (basic mode)
|
|
write_register(8'd0, 8'h1e);
|
|
|
release_rx_buffer;
|
release_rx_buffer;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
read_receive_buffer;
|
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h1, 15'h1ccf); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h1, 15'h1ccf); // mode, rtr, id, length, crc
|
read_receive_buffer;
|
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h2, 15'h73f4); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h2, 15'h73f4); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_receive_buffer;
|
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h4, 15'h37da); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h4, 15'h37da); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h5, 15'h7e15); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h5, 15'h7e15); // mode, rtr, id, length, crc
|
| Line 811... |
Line 1053... |
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
|
$display("FIFO should be full now");
|
|
|
|
// Following one is accepted with overrun
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
|
|
release_rx_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
|
// Space just enough for the following frame.
|
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
|
fifo_info;
|
|
|
|
// Following accepted with overrun
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 15);
|
read_overrun_info(0, 15);
|
|
|
release_rx_buffer;
|
release_rx_buffer;
|
release_rx_buffer;
|
release_rx_buffer;
|
|
|
release_rx_buffer;
|
release_rx_buffer;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
| Line 853... |
Line 1106... |
|
|
release_rx_buffer;
|
release_rx_buffer;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
|
clear_data_overrun;
|
|
|
release_rx_buffer;
|
release_rx_buffer;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
|
clear_data_overrun;
|
|
|
release_rx_buffer;
|
release_rx_buffer;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer;
|
| Line 881... |
Line 1138... |
|
|
release_rx_buffer;
|
release_rx_buffer;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
|
// Read irq register
|
|
read_register(8'd3);
|
|
|
|
// Read irq register
|
|
read_register(8'd3);
|
|
#1000;
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
| Line 1093... |
Line 1357... |
$display("(%0t) Tx abort requested.", $time);
|
$display("(%0t) Tx abort requested.", $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
task clear_data_overrun;
|
|
begin
|
|
write_register(8'd1, 8'h8);
|
|
$display("(%0t) Data overrun cleared.", $time);
|
|
end
|
|
endtask
|
|
|
|
|
task test_synchronization;
|
task test_synchronization;
|
begin
|
begin
|
// Hard synchronization
|
// Hard synchronization
|
#1 rx=0;
|
#1 rx=0;
|
repeat (2*BRP) @ (posedge clk);
|
repeat (2*BRP) @ (posedge clk);
|
| Line 1313... |
Line 1585... |
begin
|
begin
|
if (can_testbench.i_can_top.i_can_bsp.rx_ack &
|
if (can_testbench.i_can_top.i_can_bsp.rx_ack &
|
can_testbench.i_can_top.i_can_bsp.sample_point &
|
can_testbench.i_can_top.i_can_bsp.sample_point &
|
can_testbench.i_can_top.i_can_bsp.crc_err
|
can_testbench.i_can_top.i_can_bsp.crc_err
|
)
|
)
|
$display("(*E) (%0t) ERROR: CRC error (Calculated crc = 0x%0x, crc_in = 0x%0x)", $time, can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
|
$display("*E (%0t) ERROR: CRC error (Calculated crc = 0x%0x, crc_in = 0x%0x)", $time, can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);
|
end
|
end
|
|
|
|
|
|
|
|
|
| Line 1334... |
Line 1606... |
|
|
// form error monitor
|
// form error monitor
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (can_testbench.i_can_top.i_can_bsp.form_err)
|
if (can_testbench.i_can_top.i_can_bsp.form_err)
|
$display("(*E) (%0t) ERROR: form_error", $time);
|
$display("*E (%0t) ERROR: form_error", $time);
|
end
|
end
|
|
|
|
|
|
|
// acknowledge error monitor
|
// acknowledge error monitor
|
always @ (posedge clk)
|
always @ (posedge clk)
|
begin
|
begin
|
if (can_testbench.i_can_top.i_can_bsp.ack_err)
|
if (can_testbench.i_can_top.i_can_bsp.ack_err)
|
$display("(*E) (%0t) ERROR: acknowledge_error", $time);
|
$display("*E (%0t) ERROR: acknowledge_error", $time);
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
