| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.24 2003/02/14 20:16:53 mohor
|
|
// Several registers added. Not finished, yet.
|
|
//
|
// Revision 1.23 2003/02/12 14:28:30 mohor
|
// Revision 1.23 2003/02/12 14:28:30 mohor
|
// Errors monitoring improved. arbitration_lost improved.
|
// Errors monitoring improved. arbitration_lost improved.
|
//
|
//
|
// Revision 1.22 2003/02/11 00:57:19 mohor
|
// Revision 1.22 2003/02/11 00:57:19 mohor
|
// Wishbone interface added.
|
// Wishbone interface added.
|
| Line 167... |
Line 170... |
integer start_tb;
|
integer start_tb;
|
reg [7:0] tmp_data;
|
reg [7:0] tmp_data;
|
reg delayed_tx;
|
reg delayed_tx;
|
reg tx_bypassed;
|
reg tx_bypassed;
|
reg wb_free;
|
reg wb_free;
|
|
reg extended_mode;
|
|
|
|
|
|
|
// Instantiate can_top module
|
// Instantiate can_top module
|
can_top i_can_top
|
can_top i_can_top
|
(
|
(
|
| Line 218... |
Line 223... |
wb_we_i = 'hz;
|
wb_we_i = 'hz;
|
wb_adr_i = 'hz;
|
wb_adr_i = 'hz;
|
wb_free = 1;
|
wb_free = 1;
|
rx = 1;
|
rx = 1;
|
wb_rst_i = 1;
|
wb_rst_i = 1;
|
|
extended_mode = 0;
|
#200 wb_rst_i = 0;
|
#200 wb_rst_i = 0;
|
#200 initialize_fifo;
|
#200 initialize_fifo;
|
#200 start_tb = 1;
|
#200 start_tb = 1;
|
tx_bypassed = 0;
|
tx_bypassed = 0;
|
end
|
end
|
| Line 255... |
Line 261... |
// Set bus timing register 1
|
// Set bus timing register 1
|
write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
|
write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
|
|
|
|
|
// Set Clock Divider register
|
// Set Clock Divider register
|
write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
|
extended_mode = 1'b0;
|
|
write_register(8'd31, {extended_mode, 7'h0}); // Setting the normal mode (not extended)
|
|
|
|
|
// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
|
// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
|
/*
|
begin
|
// Set Acceptance Code and Acceptance Mask registers
|
// Set Acceptance Code and Acceptance Mask registers
|
write_register(8'd16, 8'ha6); // acceptance code 0
|
write_register(8'd16, 8'ha6); // acceptance code 0
|
write_register(8'd17, 8'hb0); // acceptance code 1
|
write_register(8'd17, 8'hb0); // acceptance code 1
|
write_register(8'd18, 8'h12); // acceptance code 2
|
write_register(8'd18, 8'h12); // acceptance code 2
|
write_register(8'd19, 8'h30); // acceptance code 3
|
write_register(8'd19, 8'h30); // acceptance code 3
|
write_register(8'd20, 8'h0); // acceptance mask 0
|
write_register(8'd20, 8'h0); // acceptance mask 0
|
write_register(8'd21, 8'h0); // acceptance mask 1
|
write_register(8'd21, 8'h0); // acceptance mask 1
|
write_register(8'd22, 8'h00); // acceptance mask 2
|
write_register(8'd22, 8'h00); // acceptance mask 2
|
write_register(8'd23, 8'h00); // acceptance mask 3
|
write_register(8'd23, 8'h00); // acceptance mask 3
|
*/
|
end
|
|
else
|
|
begin
|
|
// Set Acceptance Code and Acceptance Mask registers
|
// Set Acceptance Code and Acceptance Mask registers
|
// write_register(8'd4, 8'ha6); // acceptance code
|
|
write_register(8'd4, 8'he8); // acceptance code
|
write_register(8'd4, 8'he8); // acceptance code
|
write_register(8'd5, 8'h0f); // acceptance mask
|
write_register(8'd5, 8'h0f); // acceptance mask
|
end
|
|
|
|
#10;
|
#10;
|
repeat (1000) @ (posedge clk);
|
repeat (1000) @ (posedge clk);
|
|
|
// Switch-off reset mode
|
// Switch-off reset mode
|
| Line 294... |
Line 298... |
repeat (3) send_bit(1); // Sending Interframe
|
repeat (3) send_bit(1); // Sending Interframe
|
|
|
// test_synchronization;
|
// test_synchronization;
|
|
|
|
|
|
/*
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
|
begin
|
begin
|
// test_empty_fifo_ext; // test currently switched off
|
// test_empty_fifo_ext; // test currently switched off
|
test_full_fifo_ext; // test currently switched on
|
test_full_fifo_ext; // test currently switched on
|
// send_frame_ext; // test currently switched off
|
// send_frame_ext; // test currently switched off
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// test_empty_fifo; // test currently switched off
|
// test_empty_fifo; // test currently switched off
|
// test_full_fifo; // test currently switched off
|
// test_full_fifo; // test currently switched off
|
send_frame; // test currently switched off
|
send_frame; // test currently switched off
|
// bus_off_test; // test currently switched off
|
// bus_off_test; // test currently switched off
|
// manual_frame; // test currently switched off
|
// manual_frame; // test currently switched off
|
// forced_bus_off; // test currently switched on
|
// forced_bus_off; // test currently switched on
|
end
|
end
|
|
*/
|
|
self_reception_request;
|
|
|
$display("CAN Testbench finished !");
|
$display("CAN Testbench finished !");
|
$stop;
|
$stop;
|
end
|
end
|
|
|
| Line 368... |
Line 373... |
write_register(8'd18, 8'h00); // data byte 7
|
write_register(8'd18, 8'h00); // data byte 7
|
write_register(8'd19, 8'h00); // data byte 8
|
write_register(8'd19, 8'h00); // data byte 8
|
|
|
fork
|
fork
|
begin
|
begin
|
tx_request;
|
tx_request_command;
|
end
|
end
|
|
|
begin
|
begin
|
#2000;
|
#2000;
|
|
|
| Line 519... |
Line 524... |
|
|
|
|
|
|
fork
|
fork
|
begin
|
begin
|
tx_request;
|
tx_request_command;
|
end
|
end
|
|
|
begin
|
begin
|
#1100;
|
#1100;
|
|
|
| Line 586... |
Line 591... |
|
|
|
|
|
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
|
|
#4000000;
|
#4000000;
|
|
|
end
|
end
|
| Line 615... |
Line 620... |
write_register(8'd18, 8'h00); // data byte 7
|
write_register(8'd18, 8'h00); // data byte 7
|
write_register(8'd19, 8'h00); // data byte 8
|
write_register(8'd19, 8'h00); // data byte 8
|
|
|
fork
|
fork
|
begin
|
begin
|
tx_request;
|
tx_request_command;
|
end
|
end
|
|
|
begin
|
begin
|
#2000;
|
#2000;
|
|
|
| Line 679... |
Line 684... |
send_bit(1); // INTER
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
end // repeat
|
end // repeat
|
|
|
// Node is error passive now.
|
// Node is error passive now.
|
|
|
|
// Read irq register (error interrupt should be cleared now.
|
|
read_register(8'd3);
|
|
|
repeat (20)
|
repeat (20)
|
|
|
begin
|
begin
|
send_bit(0); // SOF
|
send_bit(0); // SOF
|
send_bit(1); // ID
|
send_bit(1); // ID
|
| Line 747... |
Line 756... |
send_bit(1); // SUSPEND
|
send_bit(1); // SUSPEND
|
end // repeat
|
end // repeat
|
|
|
// Node is bus-off now
|
// Node is bus-off now
|
|
|
|
|
|
// Read irq register (error interrupt should be cleared now.
|
|
read_register(8'd3);
|
|
|
|
|
|
|
#100000;
|
#100000;
|
|
|
// Switch-off reset mode
|
// Switch-off reset mode
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
|
|
repeat (128 * 11)
|
repeat (64 * 11)
|
|
begin
|
|
send_bit(1);
|
|
end // repeat
|
|
|
|
// Read irq register (error interrupt should be cleared now.
|
|
read_register(8'd3);
|
|
|
|
repeat (64 * 11)
|
begin
|
begin
|
send_bit(1);
|
send_bit(1);
|
end // repeat
|
end // repeat
|
|
|
|
|
|
|
|
// Read irq register (error interrupt should be cleared now.
|
|
read_register(8'd3);
|
|
|
end
|
end
|
|
|
|
|
|
|
join
|
join
|
|
|
|
|
|
|
fork
|
fork
|
begin
|
begin
|
tx_request;
|
tx_request_command;
|
end
|
end
|
|
|
begin
|
begin
|
#1100;
|
#1100;
|
|
|
| Line 829... |
Line 858... |
end
|
end
|
|
|
join
|
join
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
|
|
#4000000;
|
#4000000;
|
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
| Line 848... |
Line 877... |
|
|
|
|
task send_frame; // CAN IP core sends frames
|
task send_frame; // CAN IP core sends frames
|
begin
|
begin
|
|
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
|
if(extended_mode) // Extended mode
|
begin
|
begin
|
|
|
// Writing TX frame information + identifier + data
|
// Writing TX frame information + identifier + data
|
write_register(8'd16, 8'h12);
|
write_register(8'd16, 8'h12);
|
write_register(8'd17, 8'h34);
|
write_register(8'd17, 8'h34);
|
| Line 898... |
Line 927... |
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc
|
|
|
end
|
end
|
|
|
begin
|
begin
|
tx_request;
|
tx_request_command;
|
end
|
end
|
|
|
begin
|
begin
|
// Transmitting acknowledge
|
// Transmitting acknowledge
|
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
|
wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack);
|
| Line 913... |
Line 942... |
|
|
|
|
join
|
join
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
|
|
#200000;
|
#200000;
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
| Line 936... |
Line 965... |
end
|
end
|
endtask // send_frame
|
endtask // send_frame
|
|
|
|
|
|
|
|
task self_reception_request; // CAN IP core sends sets self reception mode and transmits a msg. This test runs in EXTENDED mode
|
|
begin
|
|
|
|
// Switch-on reset mode
|
|
write_register(8'd0, {7'h0, (`CAN_MODE_RESET)});
|
|
|
|
// Set Clock Divider register
|
|
extended_mode = 1'b1;
|
|
write_register(8'd31, {extended_mode, 7'h0}); // Setting the extended mode
|
|
|
|
// Set Acceptance Code and Acceptance Mask registers
|
|
write_register(8'd16, 8'ha6); // acceptance code 0
|
|
write_register(8'd17, 8'hb0); // acceptance code 1
|
|
write_register(8'd18, 8'h12); // acceptance code 2
|
|
write_register(8'd19, 8'h30); // acceptance code 3
|
|
write_register(8'd20, 8'h00); // acceptance mask 0
|
|
write_register(8'd21, 8'h00); // acceptance mask 1
|
|
write_register(8'd22, 8'h00); // acceptance mask 2
|
|
write_register(8'd23, 8'h00); // acceptance mask 3
|
|
|
|
// Setting the "self test mode"
|
|
write_register(8'd0, 8'h4);
|
|
|
|
// Switch-off reset mode
|
|
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
|
|
|
|
// After exiting the reset mode sending bus free
|
|
repeat (11) send_bit(1);
|
|
|
|
|
|
// Writing TX frame information + identifier + data
|
|
write_register(8'd16, 8'h45); // Frame format = 0, Remote transmision request = 1, DLC = 5
|
|
write_register(8'd17, 8'ha6); // ID[28:21] = a6
|
|
write_register(8'd18, 8'ha0); // ID[20:18] = 5
|
|
// write_register(8'd19, 8'h78); RTR does not send any data
|
|
// write_register(8'd20, 8'h9a);
|
|
// write_register(8'd21, 8'hbc);
|
|
// write_register(8'd22, 8'hde);
|
|
// write_register(8'd23, 8'hf0);
|
|
// write_register(8'd24, 8'h0f);
|
|
// write_register(8'd25, 8'hed);
|
|
// write_register(8'd26, 8'hcb);
|
|
// write_register(8'd27, 8'ha9);
|
|
// write_register(8'd28, 8'h87);
|
|
|
|
|
|
// Enabling IRQ's (extended mode)
|
|
write_register(8'd4, 8'hff);
|
|
|
|
// tx_request_command;
|
|
self_reception_request_command;
|
|
|
|
#400000;
|
|
|
|
read_receive_buffer;
|
|
release_rx_buffer_command;
|
|
release_rx_buffer_command;
|
|
read_receive_buffer;
|
|
release_rx_buffer_command;
|
|
read_receive_buffer;
|
|
release_rx_buffer_command;
|
|
read_receive_buffer;
|
|
release_rx_buffer_command;
|
|
read_receive_buffer;
|
|
|
|
|
|
read_receive_buffer;
|
|
|
|
// Read irq register
|
|
read_register(8'd3);
|
|
#1000;
|
|
|
|
end
|
|
endtask // self_reception_request
|
|
|
|
|
|
|
task test_empty_fifo;
|
task test_empty_fifo;
|
begin
|
begin
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
|
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc
|
// Enable irqs (basic mode)
|
|
write_register(8'd0, 8'h1e);
|
|
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
|
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
|
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
end
|
end
|
endtask
|
endtask
|
| Line 987... |
Line 1097... |
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
|
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
|
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
end
|
end
|
endtask
|
endtask
|
| Line 1028... |
Line 1138... |
begin
|
begin
|
|
|
// Enable irqs (basic mode)
|
// Enable irqs (basic mode)
|
write_register(8'd0, 8'h1e);
|
write_register(8'd0, 8'h1e);
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
| Line 1059... |
Line 1169... |
|
|
// Following one is accepted with overrun
|
// Following one is accepted with overrun
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
fifo_info;
|
fifo_info;
|
|
|
// Space just enough for the following frame.
|
// Space just enough for the following frame.
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
| Line 1071... |
Line 1181... |
// Following accepted with overrun
|
// Following accepted with overrun
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 15);
|
read_overrun_info(0, 15);
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 15);
|
read_overrun_info(0, 15);
|
$display("\n\n");
|
$display("\n\n");
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
clear_data_overrun;
|
clear_data_overrun_command;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
clear_data_overrun;
|
clear_data_overrun_command;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
// Read irq register
|
// Read irq register
|
read_register(8'd3);
|
read_register(8'd3);
|
| Line 1152... |
Line 1262... |
|
|
|
|
|
|
task test_full_fifo_ext;
|
task test_full_fifo_ext;
|
begin
|
begin
|
release_rx_buffer;
|
release_rx_buffer_command;
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
|
receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc
|
| Line 1178... |
Line 1288... |
fifo_info;
|
fifo_info;
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 10);
|
read_overrun_info(0, 10);
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
release_rx_buffer;
|
release_rx_buffer_command;
|
fifo_info;
|
fifo_info;
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 15);
|
read_overrun_info(0, 15);
|
$display("\n\n");
|
$display("\n\n");
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
|
|
end
|
end
|
endtask
|
endtask
|
| Line 1315... |
Line 1425... |
|
|
|
|
task read_receive_buffer;
|
task read_receive_buffer;
|
integer i;
|
integer i;
|
begin
|
begin
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
|
if(extended_mode) // Extended mode
|
begin
|
begin
|
for (i=8'd16; i<=8'd28; i=i+1)
|
for (i=8'd16; i<=8'd28; i=i+1)
|
read_register(i);
|
read_register(i);
|
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
|
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
|
$display("\nWARNING: This packet was received with overrun.");
|
$display("\nWARNING: This packet was received with overrun.");
|
| Line 1333... |
Line 1443... |
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task release_rx_buffer;
|
task release_rx_buffer_command;
|
begin
|
begin
|
write_register(8'd1, 8'h4);
|
write_register(8'd1, 8'h4);
|
$display("(%0t) Rx buffer released.", $time);
|
$display("(%0t) Rx buffer released.", $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task tx_request;
|
task tx_request_command;
|
begin
|
begin
|
write_register(8'd1, 8'h1);
|
write_register(8'd1, 8'h1);
|
$display("(%0t) Tx requested.", $time);
|
$display("(%0t) Tx requested.", $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task tx_abort;
|
task tx_abort_command;
|
begin
|
begin
|
write_register(8'd1, 8'h2);
|
write_register(8'd1, 8'h2);
|
$display("(%0t) Tx abort requested.", $time);
|
$display("(%0t) Tx abort requested.", $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task clear_data_overrun;
|
task clear_data_overrun_command;
|
begin
|
begin
|
write_register(8'd1, 8'h8);
|
write_register(8'd1, 8'h8);
|
$display("(%0t) Data overrun cleared.", $time);
|
$display("(%0t) Data overrun cleared.", $time);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
task self_reception_request_command;
|
|
begin
|
|
write_register(8'd1, 8'h10);
|
|
$display("(%0t) Self reception requested.", $time);
|
|
end
|
|
endtask
|
|
|
|
|
task test_synchronization;
|
task test_synchronization;
|
begin
|
begin
|
// Hard synchronization
|
// Hard synchronization
|
#1 rx=0;
|
#1 rx=0;
|
repeat (2*BRP) @ (posedge clk);
|
repeat (2*BRP) @ (posedge clk);
|
