| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.26 2003/02/19 14:43:17 mohor
|
|
// CAN core finished. Host interface added. Registers finished.
|
|
// Synchronization to the wishbone finished.
|
|
//
|
// Revision 1.25 2003/02/18 00:19:39 mohor
|
// Revision 1.25 2003/02/18 00:19:39 mohor
|
// Temporary backup version (still fully operable).
|
// Temporary backup version (still fully operable).
|
//
|
//
|
// Revision 1.24 2003/02/14 20:16:53 mohor
|
// Revision 1.24 2003/02/14 20:16:53 mohor
|
// Several registers added. Not finished, yet.
|
// Several registers added. Not finished, yet.
|
| Line 230... |
Line 234... |
wb_free = 1;
|
wb_free = 1;
|
rx = 1;
|
rx = 1;
|
wb_rst_i = 1;
|
wb_rst_i = 1;
|
extended_mode = 0;
|
extended_mode = 0;
|
#200 wb_rst_i = 0;
|
#200 wb_rst_i = 0;
|
#200 initialize_fifo;
|
// #200 initialize_fifo;
|
#200 start_tb = 1;
|
#200 start_tb = 1;
|
tx_bypassed = 0;
|
tx_bypassed = 0;
|
end
|
end
|
|
|
|
|
| Line 304... |
Line 308... |
// test_synchronization; // test currently switched off
|
// test_synchronization; // test currently switched off
|
// test_empty_fifo_ext; // test currently switched off
|
// test_empty_fifo_ext; // test currently switched off
|
// test_full_fifo_ext; // test currently switched off
|
// test_full_fifo_ext; // test currently switched off
|
// send_frame_ext; // test currently switched off
|
// send_frame_ext; // test currently switched off
|
// test_empty_fifo; // test currently switched off
|
// test_empty_fifo; // test currently switched off
|
// test_full_fifo; // test currently switched off
|
test_full_fifo; // test currently switched on
|
// send_frame; // test currently switched off
|
// send_frame; // test currently switched off
|
// bus_off_test; // test currently switched off
|
// bus_off_test; // test currently switched off
|
// forced_bus_off; // test currently switched off
|
// forced_bus_off; // test currently switched off
|
// send_frame_basic; // test currently switched off
|
// send_frame_basic; // test currently switched off
|
// send_frame_extended; // test currently switched off
|
// send_frame_extended; // test currently switched off
|
self_reception_request; // test currently switched on
|
// self_reception_request; // test currently switched off
|
// manual_frame_basic; // test currently switched off
|
// manual_frame_basic; // test currently switched off
|
// manual_frame_ext; // test currently switched off
|
// manual_frame_ext; // test currently switched off
|
|
|
$display("CAN Testbench finished !");
|
$display("CAN Testbench finished !");
|
$stop;
|
$stop;
|
end
|
end
|
|
|
|
|
| Line 384... |
Line 389... |
write_register(8'd16, 8'h00); // data byte 5
|
write_register(8'd16, 8'h00); // data byte 5
|
write_register(8'd17, 8'h00); // data byte 6
|
write_register(8'd17, 8'h00); // data byte 6
|
write_register(8'd18, 8'h00); // data byte 7
|
write_register(8'd18, 8'h00); // data byte 7
|
write_register(8'd19, 8'h00); // data byte 8
|
write_register(8'd19, 8'h00); // data byte 8
|
|
|
tx_bypassed = 0; // When this signal is on, tx is not looped back to the rx.
|
tx_bypassed = 1; // When this signal is on, tx is not looped back to the rx.
|
|
|
fork
|
fork
|
begin
|
begin
|
tx_request_command;
|
// tx_request_command;
|
// self_reception_request_command;
|
self_reception_request_command;
|
end
|
end
|
|
|
begin
|
begin
|
#2200;
|
#2200;
|
|
|
|
|
repeat (1)
|
repeat (1)
|
begin
|
begin
|
send_bit(0); // SOF
|
send_bit(0); // SOF
|
send_bit(0); // ID
|
send_bit(0); // ID
|
send_bit(1); // ID
|
send_bit(1); // ID
|
| Line 449... |
Line 455... |
send_bit(1); // INTER
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
send_bit(1); // INTER
|
end // repeat
|
end // repeat
|
|
|
|
|
|
|
end
|
end
|
|
|
|
|
join
|
join
|
|
|
| Line 926... |
Line 933... |
|
|
|
|
fork
|
fork
|
|
|
begin
|
begin
|
#2500;
|
#1500;
|
$display("\n\nStart receiving data from CAN bus");
|
$display("\n\nStart receiving data from CAN bus");
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc
|
| Line 1311... |
Line 1318... |
begin
|
begin
|
|
|
// Enable irqs (basic mode)
|
// Enable irqs (basic mode)
|
write_register(8'd0, 8'h1e);
|
write_register(8'd0, 8'h1e);
|
|
|
release_rx_buffer_command;
|
|
$display("\n\n");
|
$display("\n\n");
|
read_receive_buffer;
|
|
fifo_info;
|
|
|
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h1, 15'h1ccf); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h2, 15'h73f4); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h3, 15'h56a9); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h4, 15'h37da); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h4, 15'h3124); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h5, 15'h7e15); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h5, 15'h6944); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h6, 15'h39cf); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h6, 15'h5182); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h7, 15'h391d); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
$display("FIFO should be full now");
|
$display("FIFO should be full now");
|
|
|
// Following one is accepted with overrun
|
// Following one is accepted with overrun
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
|
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
fifo_info;
|
fifo_info;
|
|
|
// Space just enough for the following frame.
|
// Space just enough for the following frame.
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h0, 15'h2372); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
|
|
// Following accepted with overrun
|
// Following accepted with overrun
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 15);
|
// read_overrun_info(0, 15);
|
|
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
|
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc
|
receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h8, 15'h70e0); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 15);
|
// read_overrun_info(0, 15);
|
$display("\n\n");
|
$display("\n\n");
|
|
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
| Line 1459... |
Line 1463... |
fifo_info;
|
fifo_info;
|
receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
|
receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 10);
|
// read_overrun_info(0, 10);
|
|
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
fifo_info;
|
fifo_info;
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc
|
fifo_info;
|
fifo_info;
|
read_overrun_info(0, 15);
|
// read_overrun_info(0, 15);
|
$display("\n\n");
|
$display("\n\n");
|
|
|
release_rx_buffer_command;
|
release_rx_buffer_command;
|
read_receive_buffer;
|
read_receive_buffer;
|
fifo_info;
|
fifo_info;
|
| Line 1501... |
Line 1505... |
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
/*
|
task initialize_fifo;
|
task initialize_fifo;
|
integer i;
|
integer i;
|
begin
|
begin
|
for (i=0; i<32; i=i+1)
|
for (i=0; i<32; i=i+1)
|
begin
|
begin
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;
|
end
|
end
|
|
|
for (i=0; i<64; i=i+1)
|
for (i=0; i<64; i=i+1)
|
begin
|
begin
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
|
can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;
|
end
|
end
|
|
|
$display("(%0t) Fifo initialized", $time);
|
$display("(%0t) Fifo initialized", $time);
|
end
|
end
|
endtask
|
endtask
|
|
*/
|
|
/*
|
task read_overrun_info;
|
task read_overrun_info;
|
input [4:0] start_addr;
|
input [4:0] start_addr;
|
input [4:0] end_addr;
|
input [4:0] end_addr;
|
integer i;
|
integer i;
|
begin
|
begin
|
for (i=start_addr; i<=end_addr; i=i+1)
|
for (i=start_addr; i<=end_addr; i=i+1)
|
begin
|
begin
|
$display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
|
$display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);
|
$display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
|
$display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
*/
|
|
|
task fifo_info; // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.
|
task fifo_info; // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.
|
begin
|
begin
|
$display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
|
$display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,
|
(can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
|
(can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));
|
| Line 1598... |
Line 1602... |
|
|
|
|
task read_receive_buffer;
|
task read_receive_buffer;
|
integer i;
|
integer i;
|
begin
|
begin
|
|
$display("\n\n(%0t)", $time);
|
if(extended_mode) // Extended mode
|
if(extended_mode) // Extended mode
|
begin
|
begin
|
for (i=8'd16; i<=8'd28; i=i+1)
|
for (i=8'd16; i<=8'd28; i=i+1)
|
read_register(i);
|
read_register(i);
|
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
|
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
|
$display("\nWARNING: This packet was received with overrun.");
|
$display("\nWARNING: Above packet was received with overrun.");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
for (i=8'd20; i<=8'd29; i=i+1)
|
for (i=8'd20; i<=8'd29; i=i+1)
|
read_register(i);
|
read_register(i);
|
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
|
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun)
|
$display("\nWARNING: This packet was received with overrun.");
|
$display("\nWARNING: Above packet was received with overrun.");
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
