URL
https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 48 and 50
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Rev 50 |
Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.27 2003/03/01 22:48:26 mohor
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// Actel APA ram supported.
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//
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// Revision 1.26 2003/02/19 14:43:17 mohor
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// Revision 1.26 2003/02/19 14:43:17 mohor
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// CAN core finished. Host interface added. Registers finished.
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// CAN core finished. Host interface added. Registers finished.
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// Synchronization to the wishbone finished.
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// Synchronization to the wishbone finished.
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//
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//
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// Revision 1.25 2003/02/18 00:19:39 mohor
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// Revision 1.25 2003/02/18 00:19:39 mohor
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Line 194... |
Line 197... |
.wb_cyc_i(wb_cyc_i),
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.wb_cyc_i(wb_cyc_i),
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.wb_stb_i(wb_stb_i),
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.wb_stb_i(wb_stb_i),
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.wb_we_i(wb_we_i),
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.wb_we_i(wb_we_i),
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.wb_adr_i(wb_adr_i),
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.wb_adr_i(wb_adr_i),
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.wb_ack_o(wb_ack_o),
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.wb_ack_o(wb_ack_o),
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.clk(clk),
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.clk_i(clk),
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.rx(rx_and_tx),
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.rx_i(rx_and_tx),
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.tx(tx),
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.tx_o(tx),
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.tx_oen(tx_oen),
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.tx_oen(tx_oen),
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.irq(irq),
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.irq_o(irq),
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.clkout(clkout)
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.clkout_o(clkout)
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);
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);
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assign tx_3st = tx_oen? 1'bz : tx;
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assign tx_3st = tx_oen? 1'bz : tx;
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