URL
https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 50 and 52
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 50 |
Rev 52 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.28 2003/03/05 15:00:49 mohor
|
|
// Top level signal names changed.
|
|
//
|
// Revision 1.27 2003/03/01 22:48:26 mohor
|
// Revision 1.27 2003/03/01 22:48:26 mohor
|
// Actel APA ram supported.
|
// Actel APA ram supported.
|
//
|
//
|
// Revision 1.26 2003/02/19 14:43:17 mohor
|
// Revision 1.26 2003/02/19 14:43:17 mohor
|
// CAN core finished. Host interface added. Registers finished.
|
// CAN core finished. Host interface added. Registers finished.
|
| Line 168... |
Line 171... |
reg wb_we_i;
|
reg wb_we_i;
|
reg [7:0] wb_adr_i;
|
reg [7:0] wb_adr_i;
|
reg clk;
|
reg clk;
|
reg rx;
|
reg rx;
|
wire tx;
|
wire tx;
|
wire tx_oen;
|
|
wire wb_ack_o;
|
wire wb_ack_o;
|
wire irq;
|
wire irq;
|
wire clkout;
|
wire clkout;
|
|
|
wire tx_3st;
|
|
wire rx_and_tx;
|
wire rx_and_tx;
|
|
|
integer start_tb;
|
integer start_tb;
|
reg [7:0] tmp_data;
|
reg [7:0] tmp_data;
|
reg delayed_tx;
|
reg delayed_tx;
|
| Line 200... |
Line 201... |
.wb_adr_i(wb_adr_i),
|
.wb_adr_i(wb_adr_i),
|
.wb_ack_o(wb_ack_o),
|
.wb_ack_o(wb_ack_o),
|
.clk_i(clk),
|
.clk_i(clk),
|
.rx_i(rx_and_tx),
|
.rx_i(rx_and_tx),
|
.tx_o(tx),
|
.tx_o(tx),
|
.tx_oen(tx_oen),
|
|
.irq_o(irq),
|
.irq_o(irq),
|
.clkout_o(clkout)
|
.clkout_o(clkout)
|
);
|
);
|
|
|
assign tx_3st = tx_oen? 1'bz : tx;
|
|
|
|
|
|
// Generate wishbone clock signal 10 MHz
|
// Generate wishbone clock signal 10 MHz
|
initial
|
initial
|
begin
|
begin
|
| Line 248... |
Line 247... |
|
|
|
|
// Generating delayed tx signal (CAN transciever delay)
|
// Generating delayed tx signal (CAN transciever delay)
|
always
|
always
|
begin
|
begin
|
wait (tx_3st);
|
wait (tx);
|
repeat (4*BRP) @ (posedge clk); // 4 time quants delay
|
repeat (4*BRP) @ (posedge clk); // 4 time quants delay
|
#1 delayed_tx = tx_3st;
|
#1 delayed_tx = tx;
|
wait (~tx_3st);
|
wait (~tx);
|
repeat (4*BRP) @ (posedge clk); // 4 time quants delay
|
repeat (4*BRP) @ (posedge clk); // 4 time quants delay
|
#1 delayed_tx = tx_3st;
|
#1 delayed_tx = tx;
|
end
|
end
|
|
|
//assign rx_and_tx = rx & delayed_tx; FIX ME !!!
|
//assign rx_and_tx = rx & delayed_tx; FIX ME !!!
|
assign rx_and_tx = rx & (delayed_tx | tx_bypassed); // When this signal is on, tx is not looped back to the rx.
|
assign rx_and_tx = rx & (delayed_tx | tx_bypassed); // When this signal is on, tx is not looped back to the rx.
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.