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https://opencores.org/ocsvn/can/can/trunk
[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 59 and 60
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| Rev 59 |
Rev 60 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.30 2003/03/12 04:16:40 mohor
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// 8051 interface added (besides WISHBONE interface). Selection is made in
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// can_defines.v file.
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//
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// Revision 1.29 2003/03/05 15:33:37 mohor
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// Revision 1.29 2003/03/05 15:33:37 mohor
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// tx_o is now tristated signal. tx_oen and tx_o combined together.
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// tx_o is now tristated signal. tx_oen and tx_o combined together.
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//
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//
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// Revision 1.28 2003/03/05 15:00:49 mohor
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// Revision 1.28 2003/03/05 15:00:49 mohor
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// Top level signal names changed.
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// Top level signal names changed.
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| Line 175... |
Line 179... |
wire wb_ack_o;
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wire wb_ack_o;
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reg wb_free;
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reg wb_free;
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`else
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`else
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reg rst_i;
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reg rst_i;
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reg ale_i;
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reg ale_i;
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reg rd_i; // active low
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reg rd_i;
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reg wr_i; // active low
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reg wr_i;
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wire [7:0] port_0;
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wire [7:0] port_0;
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wire [7:0] port_0_i;
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wire [7:0] port_0_i;
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reg [7:0] port_0_o;
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reg [7:0] port_0_o;
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reg port_0_en;
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reg port_0_en;
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reg port_free;
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reg port_free;
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| Line 218... |
Line 222... |
.wb_adr_i(wb_adr_i),
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.wb_adr_i(wb_adr_i),
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.wb_ack_o(wb_ack_o),
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.wb_ack_o(wb_ack_o),
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`else
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`else
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.rst_i(rst_i),
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.rst_i(rst_i),
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.ale_i(ale_i),
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.ale_i(ale_i),
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.rd_i(rd_i), // active low
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.rd_i(rd_i),
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.wr_i(wr_i), // active low
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.wr_i(wr_i),
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.port_0_i(port_0),
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.port_0_i(port_0),
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`endif
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`endif
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.cs_can(cs_can),
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.cs_can(cs_can),
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.clk_i(clk),
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.clk_i(clk),
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.rx_i(rx_and_tx),
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.rx_i(rx_and_tx),
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| Line 277... |
Line 281... |
#200 wb_rst_i = 0;
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#200 wb_rst_i = 0;
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#200 start_tb = 1;
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#200 start_tb = 1;
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`else
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`else
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rst_i = 1'b0;
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rst_i = 1'b0;
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ale_i = 1'b0;
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ale_i = 1'b0;
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rd_i = 1'b1; // active low
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rd_i = 1'b0;
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wr_i = 1'b1; // active low
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wr_i = 1'b0;
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port_0_o = 8'h0;
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port_0_o = 8'h0;
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port_0_en = 0;
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port_0_en = 0;
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port_free = 1;
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port_free = 1;
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rst_i = 1;
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rst_i = 1;
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#200 rst_i = 0;
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#200 rst_i = 0;
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| Line 1636... |
Line 1640... |
@ (posedge clk);
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@ (posedge clk);
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#1;
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#1;
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ale_i = 0;
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ale_i = 0;
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#90; // 73 - 103 ns
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#90; // 73 - 103 ns
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port_0_en = 0;
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port_0_en = 0;
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rd_i = 0; // active low
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rd_i = 1;
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#158;
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#158;
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$display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i);
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$display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i);
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#1;
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#1;
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rd_i = 1; // active low
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rd_i = 0;
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cs_can = 0;
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cs_can = 0;
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port_free = 1;
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port_free = 1;
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end
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end
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`endif
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`endif
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endtask
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endtask
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| Line 1690... |
Line 1694... |
@ (posedge clk);
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@ (posedge clk);
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#1;
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#1;
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ale_i = 0;
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ale_i = 0;
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#90; // 73 - 103 ns
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#90; // 73 - 103 ns
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port_0_o = reg_data;
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port_0_o = reg_data;
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wr_i = 0; // active low
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wr_i = 1;
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#158;
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#158;
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wr_i = 1; // active low
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wr_i = 0;
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port_0_en = 0;
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port_0_en = 0;
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cs_can = 0;
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cs_can = 0;
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port_free = 1;
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port_free = 1;
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end
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end
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`endif
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`endif
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