URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 60 and 61

Rev 60	Rev 61
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.31 2003/03/12 04:40:00 mohor`
	`// rd_i and wr_i are active high signals. If 8051 is connected, these two signals`
	`// need to be negated one level higher.`
	`//`
`// Revision 1.30 2003/03/12 04:16:40 mohor`	`// Revision 1.30 2003/03/12 04:16:40 mohor`
`// 8051 interface added (besides WISHBONE interface). Selection is made in`	`// 8051 interface added (besides WISHBONE interface). Selection is made in`
`// can_defines.v file.`	`// can_defines.v file.`
`//`	`//`
`// Revision 1.29 2003/03/05 15:33:37 mohor`	`// Revision 1.29 2003/03/05 15:33:37 mohor`
Line 224...	Line 228...
`else	`else
`.rst_i(rst_i),`	`.rst_i(rst_i),`
`.ale_i(ale_i),`	`.ale_i(ale_i),`
`.rd_i(rd_i),`	`.rd_i(rd_i),`
`.wr_i(wr_i),`	`.wr_i(wr_i),`
`.port_0_i(port_0),`	`.port_0_io(port_0),`
`endif	`endif
`.cs_can(cs_can),`	`.cs_can_i(cs_can),`
`.clk_i(clk),`	`.clk_i(clk),`
`.rx_i(rx_and_tx),`	`.rx_i(rx_and_tx),`
`.tx_o(tx),`	`.tx_o(tx),`
`.irq_o(irq),`	`.irq_o(irq),`
`.clkout_o(clkout)`	`.clkout_o(clkout)`