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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Diff between revs 61 and 63
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| Rev 61 |
Rev 63 |
| Line 48... |
Line 48... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.32 2003/03/12 05:57:36 mohor
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// Bidirectional port_0_i changed to port_0_io.
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// input cs_can changed to cs_can_i.
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//
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// Revision 1.31 2003/03/12 04:40:00 mohor
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// Revision 1.31 2003/03/12 04:40:00 mohor
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// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
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// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
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// need to be negated one level higher.
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// need to be negated one level higher.
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//
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//
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// Revision 1.30 2003/03/12 04:16:40 mohor
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// Revision 1.30 2003/03/12 04:16:40 mohor
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| Line 1636... |
Line 1640... |
wait (port_free);
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wait (port_free);
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port_free = 0;
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port_free = 0;
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@ (posedge clk);
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@ (posedge clk);
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#1;
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#1;
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cs_can = 1;
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cs_can = 1;
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@ (negedge clk);
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#1;
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ale_i = 1;
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ale_i = 1;
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port_0_en = 1;
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port_0_en = 1;
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port_0_o = reg_addr;
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port_0_o = reg_addr;
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@ (posedge clk);
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@ (negedge clk);
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#1;
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#1;
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ale_i = 0;
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ale_i = 0;
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#90; // 73 - 103 ns
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#90; // 73 - 103 ns
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port_0_en = 0;
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port_0_en = 0;
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rd_i = 1;
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rd_i = 1;
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| Line 1690... |
Line 1696... |
wait (port_free);
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wait (port_free);
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port_free = 0;
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port_free = 0;
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@ (posedge clk);
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@ (posedge clk);
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#1;
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#1;
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cs_can = 1;
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cs_can = 1;
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@ (negedge clk);
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#1;
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ale_i = 1;
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ale_i = 1;
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port_0_en = 1;
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port_0_en = 1;
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port_0_o = reg_addr;
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port_0_o = reg_addr;
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@ (posedge clk);
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@ (negedge clk);
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#1;
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#1;
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ale_i = 0;
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ale_i = 0;
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#90; // 73 - 103 ns
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#90; // 73 - 103 ns
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port_0_o = reg_data;
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port_0_o = reg_data;
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wr_i = 1;
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wr_i = 1;
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