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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench_defines.v] - Diff between revs 11 and 13
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/01/08 02:09:44 mohor
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// Acceptance filter added.
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//
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// Revision 1.3 2002/12/28 04:13:53 mohor
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// Revision 1.3 2002/12/28 04:13:53 mohor
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// Backup version.
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// Backup version.
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//
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//
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// Revision 1.2 2002/12/27 00:12:48 mohor
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// Revision 1.2 2002/12/27 00:12:48 mohor
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// Header changed, testbench improved to send a frame (crc still missing).
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// Header changed, testbench improved to send a frame (crc still missing).
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`define CAN_TIMING1_TSEG1 4'h4 // TSEG1 segment (value+1)
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`define CAN_TIMING1_TSEG1 4'h4 // TSEG1 segment (value+1)
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`define CAN_TIMING1_TSEG2 3'h3 // TSEG2 segment (value+1)
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`define CAN_TIMING1_TSEG2 3'h3 // TSEG2 segment (value+1)
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`define CAN_TIMING1_SAM 1'h0 // Triple sampling
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`define CAN_TIMING1_SAM 1'h0 // Triple sampling
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// Clock Divider register
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// Clock Divider register
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`define CAN_CLOCK_DIVIDER_MODE 1'h1 // Normal (not extended mode
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`define CAN_CLOCK_DIVIDER_MODE 1'h0 // 0 - Normal mode, 1 - Extended mode
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