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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2003/01/09 14:46:52 mohor
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// Temporary files (backup).
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//
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// Revision 1.4 2003/01/08 02:09:44 mohor
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// Revision 1.4 2003/01/08 02:09:44 mohor
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// Acceptance filter added.
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// Acceptance filter added.
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//
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//
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// Revision 1.3 2002/12/28 04:13:53 mohor
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// Revision 1.3 2002/12/28 04:13:53 mohor
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// Backup version.
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// Backup version.
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//
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//
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//
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//
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//
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//
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//
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//
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// Mode register
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/* Mode register */
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`define CAN_MODE_RESET 1'h1 // Reset mode
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`define CAN_MODE_RESET 1'h1 /* Reset mode */
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/* Bit Timing 0 register value */
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`define CAN_TIMING0_BRP 6'h1 /* Baud rate prescaler (2*(value+1)) */
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`define CAN_TIMING0_SJW 2'h2 /* SJW (value+1) */
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/* Bit Timing 1 register value */
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`define CAN_TIMING1_TSEG1 4'h4 /* TSEG1 segment (value+1) */
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`define CAN_TIMING1_TSEG2 3'h3 /* TSEG2 segment (value+1) */
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`define CAN_TIMING1_SAM 1'h0 /* Triple sampling */
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// Bit Timing 0 register value
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/* Clock Divider register */
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`define CAN_TIMING0_BRP 6'h1 // Baud rate prescaler (2*(value+1))
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`define CAN_CLOCK_DIVIDER_MODE 1'b0 /* 0 - Normal mode, 1 - Extended mode */
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`define CAN_TIMING0_SJW 2'h2 // SJW (value+1)
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// Bit Timing 1 register value
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`define CAN_TIMING1_TSEG1 4'h4 // TSEG1 segment (value+1)
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`define CAN_TIMING1_TSEG2 3'h3 // TSEG2 segment (value+1)
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`define CAN_TIMING1_SAM 1'h0 // Triple sampling
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// Clock Divider register
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`define CAN_CLOCK_DIVIDER_MODE 1'h0 // 0 - Normal mode, 1 - Extended mode
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No newline at end of file
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No newline at end of file
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