URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench_defines.v] - Diff between revs 28 and 37

Rev 28	Rev 37
Line 48...	Line 48...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.7 2003/02/09 02:24:11 mohor`
	`// Bosch license warning added. Error counters finished. Overload frames`
	`// still need to be fixed.`
	`//`
`// Revision 1.6 2003/01/14 12:19:29 mohor`	`// Revision 1.6 2003/01/14 12:19:29 mohor`
`// rx_fifo is now working.`	`// rx_fifo is now working.`
`//`	`//`
`// Revision 1.5 2003/01/09 14:46:52 mohor`	`// Revision 1.5 2003/01/09 14:46:52 mohor`
`// Temporary files (backup).`	`// Temporary files (backup).`
Line 82...	Line 86...
`/* Bit Timing 1 register value */`	`/* Bit Timing 1 register value */`
`define CAN_TIMING1_TSEG1 4'h4 /* TSEG1 segment (value+1) */	`define CAN_TIMING1_TSEG1 4'h4 /* TSEG1 segment (value+1) */
`define CAN_TIMING1_TSEG2 3'h3 /* TSEG2 segment (value+1) */	`define CAN_TIMING1_TSEG2 3'h3 /* TSEG2 segment (value+1) */
`define CAN_TIMING1_SAM 1'h0 /* Triple sampling */	`define CAN_TIMING1_SAM 1'h0 /* Triple sampling */

`/* Clock Divider register */`
`define CAN_CLOCK_DIVIDER_MODE 1'b0 /* 0 - Normal mode, 1 - Extended mode */


`No newline at end of file`	`No newline at end of file`